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429NEW-03-15
429总线通过FPGA直接实现发送程序,通过Verilog实现(send 429 message by Verilog and FPGA )
- 2021-04-23 09:58:48下载
- 积分：1
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lab2
说明： 使用vivado和Xilinx开发板实现抢答器，开发板为Xilinx Artix-7(Using vivado and Xilinx development board to achieve the responder, the development board is Xilinx artix-7)
- 2021-04-23 01:58:48下载
- 积分：1
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ad7606
ADC7606的驱动代码，采用verilog实现(ADC7606 driver code, using Verilog to achieve)
- 2021-03-30 09:39:10下载
- 积分：1
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through CPLD to eight parallel data into serial data and methods can be used I2C...
通过CPLD将8位并行数据转换为串行数据并可以采用I2C方式与其他器件连接，可以用于MCU需要与提供I2C接口器件通信的场合。-through CPLD to eight parallel data into serial data and methods can be used I2C connections with other devices, which can be used to provide MCU with I2C Interface Communications occasions.
- 2022-05-30 15:43:30下载
- 积分：1
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irda.tar
depends on irda transmitter recever
- 2009-11-20 00:31:48下载
- 积分：1
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hanming
用Verilog语言实现汉明编码，很粗燥，是大三的时候做的(With the Verilog language Hamming code, it is rough dry, a junior at the time to do)
- 2010-10-01 13:08:16下载
- 积分：1
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SPI
design and implement a digital system on the Altera NIOS board which will read an analogue input using MicroChip’s SPI MCP3202 12-Bit A/D converter. The 8 most significant bits of the converted data will be displayed on two seven segments of the NIOS development board. The sampling frequency is 20kHZ. Use a potentiometer.(design and implement a digital system on the Altera NIOS board which will read an analogue input using MicroChip' s SPI MCP3202 12-Bit A/D converter. The 8 most significant bits of the converted data will be displayed on two seven segments of the NIOS development board . The sampling frequency is 20kHZ. Use a potentiometer.)
- 2010-08-17 19:16:12下载
- 积分：1
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cycloneII Quartus verilog to develop a simple sequential circuit
cycloneII Quartus verilog开发的简单时序电路-cycloneII Quartus verilog to develop a simple sequential circuit
- 2022-03-01 09:19:56下载
- 积分：1
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Cadence VHDL Operational the package, seeking to achieve root, You are not squar...
Cadence的VHDL运算库包，实现求方根，平方你是不是以前不知道怎么弄．哈哈．-Cadence VHDL Operational the package, seeking to achieve root, You are not square did not know how get. Ha ha.
- 2022-08-16 03:35:39下载
- 积分：1
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用VHDL语言编写的一个控制程序，主要功能是输入码同步，输出字和帧信号...
用VHDL语言编写的一个控制程序，主要功能是输入码同步，输出字和帧信号-VHDL language using a control program, the main function is to input code synchronization, and frame signals output word
- 2023-04-27 22:40:03下载
- 积分：1
