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可配置CRC参考设计 xilinx提供的VHDL
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高级verilog编程实现讲义，全英文讲义
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VHDL_COUNTING 0_9_LED 7 段 (ĐẾM 0 ĐẾN 9 HIỂN THỊ LED 7 ĐOẠN BẰNG NGÔN NGỮ VHDL)
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This is is a bridge IP core to interface the Tensilica PIF bus protocol with the...
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固定的点复杂 FFT
固定的 128 点复杂 FFT
或
64/8/16 点
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CH4CH2CH1VHDL 数字电路参考书所有程序8
CH4CH2CH1VHDL 数字电路参考书所有程序8-CH4CH2CH1VHDL digital circuit reference all proceedings 8
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rs_encoder
RS编码器的fpga实现，有TESTBench(RS encoder to achieve the fpga, and TESTBench)
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ram32b
VHDL code for 32 byte RAM
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m68000
VHDL code for MC68000
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6通道正弦波发生器，产生频率，相位，幅值都可调的正弦波形...
6通道正弦波发生器，产生频率，相位，幅值都可调的正弦波形-6-channel sine wave generator, resulting in frequency, phase, amplitude of the sinusoidal waveform are adjustable
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