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ads8361_avl
Interface for ADS8361 TI ADC
IP Core for ALTERA NIOS2
- 2013-04-04 16:12:13下载
- 积分：1
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verilog时钟分频器~ 50hmz波特率9600bps，使用~
verilog分频器～时钟为50hmz，波特率采用9600bps～-Verilog clock divider ~ 50hmz, using baud rate 9600bps ~
- 2022-06-03 13:21:28下载
- 积分：1
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VLSI implementation of high speed and high resolution FFT algorithm based on Rad...
VLSI implementation of high speed and high resolution FFT algorithm based on Radix 2 for DSP application
- 2022-05-07 09:52:02下载
- 积分：1
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LDPC
LDPC Encoding Ebook Tetourial code
- 2021-03-23 08:49:15下载
- 积分：1
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To increase simulation speed, ModelSim® can apply a variety of optimizations...
To increase simulation speed, ModelSim® can apply a variety of optimizations to your design. These include, but are not limited to, mergingprocesses, pulling constants out of loops, clock suppression, and signal collapsing. You control the level of optimization by specifying certain switches when you invoke the compiler.
- 2022-03-06 09:05:21下载
- 积分：1
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zixiechengxu
用verilog编写的包含有与DSP通信，三电平svpwm实现的程序，(Written in verilog contains communicate with the DSP, three-level svpwm realize the procedures)
- 2021-04-18 15:28:51下载
- 积分：1
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lpddr2
LPDDR2 SDRAM memories compliant to JEDEC JESD209-2.
- 2015-05-11 20:57:21下载
- 积分：1
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Verilog HDL 频率可调的任意波形发生器
Verilog HDL数字系统设计项目，频率可调的任意波形发生器，可以输出正弦波、方波、三角波和反三角四种波形(Verilog HDL digital system design projects, adjustable frequency arbitrary waveform generator can output sine wave, square wave, triangle wave and the anti-triangular four waveform)
- 2011-05-08 03:21:34下载
- 积分：1
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pipeline_FPGA
FPGA流水线设计的资料，可以作为学习FPGA开发并行操作的一个经典教材，具有很好的指导作用。(FPGA pipeline design information can be developed as a learning FPGA parallel operation of a classic textbook, has a good guide.)
- 2011-07-02 12:00:57下载
- 积分：1
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HDB3 ENCODING AND DECODING METHOD
HDB3 ENCODING AND DECODING METHOD
- 2022-12-23 08:30:03下载
- 积分：1
