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LDPCtest
ldpc编码器ru算法的verilog语言的完整实现，希望对您有用(ldpc encoder, RU, VERILOG，altera)
- 2021-01-07 14:08:53下载
- 积分：1
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实用的程序代码，希望对大家有用，已经调试通过
实用的程序代码，希望对大家有用，已经调试通过-Practical program code, in the hope that useful to everybody, has debugging through
- 2022-03-23 06:26:50下载
- 积分：1
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小波变换去噪vhdl
基于小波变换去噪，采用了vhdl编写，已经在和matlab上对比过，结果准确，而且大量的节约了时间，欢迎下载，可以在quartusii中查看RTL电路，可以在modesim中仿真出结果
- 2022-02-20 11:22:37下载
- 积分：1
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prj_ex_5
自动化仿真平台的搭建使用代码，经过具体的仿真和优化，发现代码完全可用(The automated simulation platform is built using code, and after specific simulation and optimization, it is found that the code is fully available)
- 2017-09-21 15:11:33下载
- 积分：1
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sp6ex15
SRAM读写测试，每秒进行一次单字节SRAM读写，使用chipscope观察时序波形(SRAM read and write test, a single byte SRAM read and write every second, using chipscope to observe the timing waveform)
- 2017-08-02 10:29:57下载
- 积分：1
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fpga_sdram_inst
nios学习资料，fpga调用外部sdram实例，值得初学者下载。(nios learning materials, fpga call external sdram instance, it is worth beginners to download.)
- 2013-08-24 22:26:31下载
- 积分：1
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VHDL实现 8051 CPU核 Oregano Systems 8
VHDL实现 8051 CPU核 Oregano Systems 8-bit Microcontroller IP-Core-VHDL 8051 CPU nuclear Oregano Systems 8-bit Mic rocontroller IP-Core
- 2022-01-21 00:52:30下载
- 积分：1
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airthmatic & logic unit
airthmatic & logic unit
- 2023-02-23 08:10:03下载
- 积分：1
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fulladd
this files in Quartus2 are fulladder
- 2016-05-17 16:38:42下载
- 积分：1
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索FPGA Verilog使用ROM和RAM实现高dcfifo
alteral FPGA VERILOG 利用 ROM DCFIFO 和RAM
实现高速到低速时钟域的数据传输 ，值得学习。-alteral FPGA VERILOG using ROM DCFIFO and RAM to realize high-speed low-speed clock domain data transfer, it is worth learning.
- 2023-05-06 14:25:03下载
- 积分：1
