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8b10b_xilinx
xilinx 的8B10B编解码源码, 里面有仿真模型,用以测试验证(xilinx 8B10B encode/decode source)
- 2018-07-20 16:02:29下载
- 积分：1
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fpga超声波测距
FPGA开发超声波测距，可改写工业探伤或倒车测距等系统，quartus2下选择EP2C5Q208C8（CycloneⅡ） 支持目前淘宝上能买到的所有4-5针超声波模块 应用cycloneⅡ自带除法模块 开发板为有光技术YG2.1 生成电路规模较小 ！！注意：移植程序仅需重新约束数码管和超声波模块的针脚
(Ultrasonic Ranging FPGA development, industrial inspection or reverse rewritable ranging systems, EP2C5Q208C8 (CycloneⅡ) under quartus2 4-5 needle ultrasonic module supports all currently scouring the treasure can buy Applications cycloneⅡ own division module Development board bright technical YG2.1 Small scale generating circuit ! ! Note: The migration program only re-constraint digital and ultrasonic modules Pin)
- 2022-07-17 19:43:35下载
- 积分：1
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altera公司cpld的原理图库(protel格式)
altera公司cpld的原理图库(protel格式)-sch.lib about altera s cpld.
- 2022-03-18 02:53:20下载
- 积分：1
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千年工具大全
说明： 千年服务端修改工具，千年db数据在线修改(Millennium server modification tool
Millennium server modification tool)
- 2020-07-07 15:58:57下载
- 积分：1
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This is a use of Xilinx macroblaze the user program will read from flash memory...
这是一个利用xilinx的macroblaze将用户程序由flash读取至ddr内存的例程，关键是bootloader的写法。-This is a use of Xilinx macroblaze the user program will read from flash memory to ddr routine, the key is the wording of bootloader.
- 2022-03-22 13:26:24下载
- 积分：1
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emif_tt
实现dsp与fpga的emif的verilog异步实现，可实现异步读写以及相应功能模块控制，文件中包含仿真后的波形图形以及仿真测试程序，运行环境quartus ii11.0，仿真环境mmodelsim se 6.5d(Achieve dsp and fpga verilog asynchronous implementation of the emif, enabling asynchronous reading and writing as well as the corresponding function module control, the document contains graphics, and after the simulation waveform simulation testing procedures, operating environment quartus ii11.0, simulation environment mmodelsim se 6.5d)
- 2020-12-04 15:59:23下载
- 积分：1
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source
说明： I2C MASTER DESIGNED by Verilog
- 2020-06-18 23:40:02下载
- 积分：1
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8位大小比较器的VHDL源代码，Magnitude Comparator
VHDL description of a 4...
8位大小比较器的VHDL源代码，Magnitude Comparator
VHDL description of a 4-bit magnitude comparator with expansion inputs-eight compared with the size of the VHDL source code, Magnitude Comparator VHDL description of a 4-bit magnitude comparator inputs with expansion
- 2023-07-28 13:55:03下载
- 积分：1
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SDC_RDC
基于FPGA的双通道旋转变压器测角系统硬件设计，分析的比较清楚。(FPGA based dual channel rotary transformer angle measurement system hardware design, analysis of the relatively clear.)
- 2011-08-07 20:23:10下载
- 积分：1
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16*16点阵显示”北京欢迎"
提供2个VHDL程序实现键盘显示的功能，第一个是16*16点阵显示“北京欢迎”，用VHDL语言编程实现，串烧在单片机实验工具箱上，让单片机点阵键盘上依次显示“北京欢迎”的字样。另附有LED数码管循环显示0～9数字的VHDL程序 ，成功串烧后，键盘上连续显示0~9这10个数字。
- 2022-08-03 09:36:55下载
- 积分：1
