-
Mano-CPU_VHDL-Implementation
Mano s cpu for Man s instructions
- 2012-04-28 01:04:57下载
- 积分:1
-
hdb3a
快速实现HDB3码与普通码二进制码的转换,方便学习与了解HDB3码的转换(Quickly achieve HDB3 code and common code binary code conversion, facilitate learning and understanding HDB3 code conversion)
- 2020-11-09 15:09:48下载
- 积分:1
-
VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用
VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用-CARDBUS IP CORE
- 2022-03-12 11:28:40下载
- 积分:1
-
verilog编写的32位浮点加法器
verilog编写的32位浮点加法器-32-bit Floating Point Addition Written in Verilog
- 2022-02-21 08:09:50下载
- 积分:1
-
GF_2_m_域乘法器的快速设计及FPGA实现,对于rs编翼码的理解和设计有帮助...
GF_2_m_域乘法器的快速设计及FPGA实现,对于rs编翼码的理解和设计有帮助-Domain multiplier GF_2_m_ rapid design and FPGA realization for rs wing made the understanding of code and design has helped
- 2022-04-25 05:12:28下载
- 积分:1
-
用vhdl描写的通用异步改进dram控制器,经过编译器综合和仿真测试,符合设计要求。...
用vhdl描写的通用异步改进dram控制器,经过编译器综合和仿真测试,符合设计要求。-Using VHDL description Universal Asynchronous improved dram controller, through an integrated compiler and simulation testing, in line with the design requirements.
- 2022-04-19 09:59:57下载
- 积分:1
-
400rdm
用于FPGA的学习,大家值得借鉴,可以好好学习一下(this is for fpga and you can use this.)
- 2020-06-16 15:20:02下载
- 积分:1
-
alpha011410
Firmware setopbox Ali3329B
- 2016-04-03 19:16:28下载
- 积分:1
-
正弦波在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过...
正弦波在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-sine wave in dspbuilder under VHDL source code and test incentives document matl ab model, the simulation under through modelsim
- 2023-07-26 10:55:02下载
- 积分:1
-
FPGA——IP_RAM实验
说明: FPGA——IP_RAM实验:
创建IPRAM核,单端口,10位地址线(256字节),8位数据线(每字节8byte),读写使能
input [9:0] address;
input clock;
input [7:0] data;
input wren; //置1则写入
output [7:0] q;
LNXmode:控制LEDC显示
1:mode1,从k1~k3输入data的低4位,ledb计时,从0~f,计时跳变沿读取k1~k3的值,存入RAM
8个数之后,从RAM输出数据,用leda显示,同样每秒变化一次(The experiment of FPGA-IP_RAM:
Create IPRAM core, single port, 10 bit address line (256 bytes), 8 bit data line (8 byte per byte), read and write enablement)
- 2020-06-22 04:20:02下载
- 积分:1