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clock_gyc_system
基于用户自定义模块的实时时钟的设计;Qsys硬件设计;(Custom real-time clock module-based design Qsys hardware design )
- 2020-12-23 09:19:08下载
- 积分:1
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hdl-master
ADI ad9361 vivado 下源代码(ADI ad9361 vivado source code)
- 2015-08-30 21:39:28下载
- 积分:1
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CORDIC_vhdl
基于VHDL语言的CORDIC算法实现,用于计算sin(x),cos(x)等,实测可用(Based on VHDL CORDIC algorithm, used to calculate sin (x), cos (x), etc., the measured available)
- 2020-11-27 22:19:31下载
- 积分:1
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AHB2APB Bridge 的Verilog
在AMBA bus 总线中,AHB是高速的总线接口,APB则是低速的总线接口,有些低速的外设不需要接入高速的外设时,便通过桥接的方式接入APB总线中。
- 2022-01-20 22:42:04下载
- 积分:1
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7_ImageEnhance
基于System Generator的图像处理工程,多媒体处理FPGA实现的源码,图像增强处理,平滑,锐化,滤波(System Generator based image processing engineering, multimedia processing FPGA implementation source code, image enhancement, smoothing, sharpening, filtering)
- 2020-10-20 21:07:24下载
- 积分:1
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AHB总线系统的设计和仿真
资源描述详细的阅读了AHB协议规范,采用Verilog硬件描述语言,按照协议要求设计主机与从机。时序仿真通过。在压缩包里附有该设计的验证程序。
- 2022-03-24 01:13:49下载
- 积分:1
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v5_emac
以太网的FPGA程序实现以太网的FPGA程序实现以太网的FPGA程序实现(enternet verilog fpga)
- 2013-12-15 23:08:11下载
- 积分:1
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12
说明: 用FPGA进行等精度频率和相位差测量的程序,本程序是在EPEC6Q240C8下的程序(Carried out with the FPGA such as the frequency and phase measurement precision of the procedure, this procedure was the procedure under the EPEC6Q240C8)
- 2010-03-03 17:42:11下载
- 积分:1
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FPGA 64位除法器 verilog
用verilog语言实现的除法器,实现方式为移位减
- 2023-09-02 08:35:03下载
- 积分:1
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bark_filter_banks
自写的巴克频带滤波器组代码,生成频带滤波器组。内涵debug:输出生成的滤波器(Barker band filter bank code that generates band filter bank. Connotation debug: output generated filter)
- 2013-08-26 13:55:18下载
- 积分:1