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DTMB
能够完美产生数字地面电视(DTMB)的信源的程序。帧头模式为模式一。信道可选择,信号加入频偏,延时,后经滤波器后输出。(Able to produce perfect digital terrestrial television (DTMB) of the source program. Mode is the mode a header. Channels to choose from, the signal adding offset, delay, after the filter output.)
- 2013-07-25 11:22:28下载
- 积分:1
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uart-for-fpga
说明: Simple UART for FPGA is UART (Universal Asynchronous Receiver & Transmitter) controller for serial communication with an FPGA. The UART controller was implemented using VHDL 93 and is applicable to any FPGA.
Simple UART for FPGA requires: 1 start bit, 8 data bits, 1 stop bit!
The UART controller was simulated and tested in hardware.
- 2020-06-24 22:00:02下载
- 积分:1
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多周期CPU设计包括basys3板的设计
都是实验课作业,直接打包的文件,下载之后可以直接跑。
- 2022-10-18 23:25:05下载
- 积分:1
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verilogdct
dct实现verilog hdl的数字图像处理,源代码(dct achieve verilog hdl digital image processing, source code)
- 2020-12-02 17:49:26下载
- 积分:1
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steper motor
说明: stepper motor module on spartan 6 and 24MHz clock fequency
- 2019-03-10 15:44:31下载
- 积分:1
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FSK
2FSK的matlab仿真,叠加了高斯白噪声(2FSK matlab simulation, superimposed on a Gaussian white noise)
- 2021-04-13 02:58:56下载
- 积分:1
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DA模块(TLC5620)、AD模块(TLV1544)
//顶层模块
//本次正弦波频率大约在750-800Hz,没有精确计算,和DA的加载时间有关
module DA_AD
(
clk,
rst_n,
DAC_SCLK,
DAC_DATA,
DAC_LDAC,
DAC_LOAD,
ADC_SDO,
ADC_SDI,
ADC_SCLK,
ADC_EOC,
ADC_CS,
ADC_FS,
led1
);
input clk;
input rst_n;
output DAC_SCLK;
output DAC_DATA;
output DAC_LDAC;
output DAC_LOAD;
//AD相关
input ADC_SDO; //ADC转换完成输出的数据
input ADC_EOC; //ADC的转换完成输出信号
output ADC_SDI; //ADC的输入数据
output ADC_SCLK; //ADC时钟信号
output ADC_CS; //ADC片选,低有效
output ADC_FS; //DSP模式帧起始信号
output led1;
wire DATA_EN;
wire [7:0] Cordic2driver;
wire start;
TLC5620_driver ins_TLC5620_driver
(
.clk(clk),
.rst_n(rst_n),
.DATA_IN(Cordic2driver),
.DATA_EN(DATA_EN),
.
- 2022-02-05 07:51:39下载
- 积分:1
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Manchester-code-of-VHDL-program
利用FPGA实现硬件的VHLD语言的Manchester code。(Hardware implementation using FPGA VHLD language Manchester code.)
- 2013-07-14 22:08:25下载
- 积分:1
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I2C 异步子设备
这代码是 I2C 子设备。给定的 I2C 设备是异步的可以用来通电,数字逻辑的其余部分。也可以用作 SMBus 设备。
- 2023-08-18 13:55:03下载
- 积分:1
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04_uart_test
说明: 基于FPGA的串口发送和接收,使用的verlilog语言(Using Verilog serial port program, send and receive.)
- 2020-10-13 10:33:10下载
- 积分:1