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基于ALtera公司的若干款FPGA的调试经验，对初学者有重要价值
基于ALtera公司的若干款FPGA的调试经验，对初学者有重要价值-ALtera a number of sections based on the company" s FPGA debugging experience, great value for beginners
- 2022-05-19 11:30:26下载
- 积分：1
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OFDM-system-FPGA-design
说明： OFDM基带处理的书籍和论文，以及发送和接收端源码。(OFDM baseband processing books and papers, as well as send and receive source code.)
- 2020-06-06 13:54:22下载
- 积分：1
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RTC
verilog编写的RTC（实时时钟）包含APB总线接口、时钟计时部分等(verilog prepared by the RTC (real time clock) contains APB bus interface, clock time some other)
- 2009-12-19 23:51:50下载
- 积分：1
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vhdl adder with two input 4
vhdl adder with two input 4-bit and output of 4 bits and carry
- 2022-11-16 00:35:03下载
- 积分：1
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9. For the key to enter a password lock, assuming that reset after the seven lam...
9对于输入密码锁的键，假设复位后七个灯显示" 0"，使用sw1、sw2、sw3、sw4 4，只需按下并松开任意sw1、sw2键，使七个灯显示值加" 1"，只要按下并松开任意sw3、sw4，将使七个灯显示值加" 2"
- 2022-10-18 01:25:04下载
- 积分：1
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fifo
一个FIFO产生程序，主要是一个格雷码的加法器(A FIFO generation process, is primarily a gray code adder)
- 2011-08-28 10:39:31下载
- 积分：1
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S05_example_Network
说明： vivado lwip 应用文档 基于zynq 7020(vivado lwip example text of zynq)
- 2020-06-17 11:40:02下载
- 积分：1
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key_test
fpga的按键程序，实现按键和led的对应点亮。(The key program of FPGA realizes the corresponding lighting between keys and led.)
- 2018-04-13 00:00:28下载
- 积分：1
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ROM的4位的话。
4 bit ROM for Quartus
- 2022-01-30 19:14:13下载
- 积分：1
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liuy
一个精确时钟的v-log程序，只用一个全局时钟，增加了精确度(An accurate clock in the v-log program, only one global clock, increased accuracy)
- 2010-08-25 12:26:25下载
- 积分：1
