用verilog语言写的串口通信程序,包括收发两个模块,可用于FPGA的通信中,可通过程序设置收发的位数,有很好的扩展性.-Verilog language used to write serial communication program, including the sending and receiving two modules can be used for FPGA communications, you can send and receive through the program to set the number of bits, there is a very good scalability.

说明：  适合入门及进阶的100个VHDL练习题，从易到难(100 VHDL exercises for beginners and advanced students, from easy to difficult)

多相抽取滤波器。分四相，两倍抽取，采用16阶FIR滤波器实现(Polyphase decimation filters. Divided into four phases, extracted twice using 16-order FIR filter implementation)

用FPGA中的三速以太网来实现UDP通信，功能强大(With a triple-speed Ethernet in the FPGA to implement UDP communication, powerful)

DDS VHDL include everything of dds AD9914

VHDL Design of BCD to 7-segment decoder using PROM

采用VHDL编写的频率计，模块划分清晰易懂，基本原理为检测一个闸门脉冲周期内的信号次数，采用四段数码管显示

产生VGA彩条信号(Verilog 语言）-Generate VGA signal

说明：  verilog语言编写的简单FPGA 的从机模式 spi 通讯(Slave mode SPI communication of FPGA)

利用8段数码管实现的秒表时钟，FPGA使用EP2C80208C8N，通过例化数码管控制模块、秒表计时模块、时钟进位模块等实现准确计时。