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VHDL_APPOINTMENT TIME(Hẹn thời gian hiển thị LCD sử dụng ngôn ngữ VHDL)
VHDL_APPOINTMENT TIME(Hẹn thời gian hiển thị LCD sử dụng ngôn ngữ VHDL)
- 2022-01-25 18:25:54下载
- 积分：1
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PipelineSim
一个计算机原理课程设计的作业，5级流水线CPU，指令集到代码均为自己设计，有最终报告文档，组建说明，并行除法，16位字长，定长指令，Verilog源代码，顶层设计图。结构简单，冲突解决方式也很简单，代码量小。(A computer theory course design work, five pipelined CPU, instruction set to the code are design, the final report documents the formation of parallel division, 16-bit word length, fixed-length instructions, Verilog source code, top level design. Simple structure, conflict resolution is also very simple, a small amount of code.)
- 2012-06-24 22:19:14下载
- 积分：1
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数字频率计
该项目用来测量频率。它有三个范围，其中包括 0.01 赫兹 ~ 1 Hz，1 ~ 100 Hz 和 100 ～ 10000 Hz。这样的结果将是最好的程序能自动调节到最佳的范围内。这个项目是在 Altera 软件 8.1 上进行验证。
- 2022-08-26 07:45:48下载
- 积分：1
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DE0-PWM-Led-Drive---simulation
DE0_PWM_LED_DRİ VE_Sİ MULATİ ON
- 2015-12-04 16:32:56下载
- 积分：1
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multi16
有符号16位乘法器。经典booth编码。拓扑结构为wallance树。加法器类型是进位选择加法器。(Number system: 2 s complement
Multiplicand length: 16
Multiplier length: 16
Partial product generation: PPG with Radix-4 modified Booth recoding
Partial product accumulation: Wallace tree
Final stage addition: Carry select adder
)
- 2013-01-01 14:13:58下载
- 积分：1
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e2
Any change to the value of Mresults in immediate and phase-continuous changes in the output frequency
- 2014-02-23 02:42:47下载
- 积分：1
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基于FPGA的高性能32位浮点FFTIP核的开发，适合fpga工程技术人员参考...
基于FPGA的高性能32位浮点FFTIP核的开发，适合fpga工程技术人员参考-FPGA-based high-performance 32-bit floating-point nuclear FFTIP development, engineering and technical personnel for reference fpga
- 2022-10-24 15:10:04下载
- 积分：1
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业界标准的Verilog语法格式
说明： verilog标准语法，还有很多的样例参考，学习的好资料。(Verilog standard grammar, there are many examples for reference, good learning materials.)
- 2020-06-15 22:50:02下载
- 积分：1
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VHDL_freerisc8
说明： 一个8位RiSC单片机的VHDL代码，
具有很好的参考价值。(an eight RiSC SCM VHDL code, is a good reference value.)
- 2006-02-15 10:58:14下载
- 积分：1
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一个verilog语言描写的同步fifo,包括:Fifo using declared registers for storage和Fifo using (mo...
一个verilog语言描写的同步fifo,包括:Fifo using declared registers for storage和Fifo using (model of) standard memory chip for storage.两种方式,包含testbench-Verilog language describes a synchronous fifo, including: Fifo using declared registers for storage and Fifo using (model of) standard memory chip for storage. In two ways, including Testbench
- 2022-08-21 18:15:23下载
- 积分：1
