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可编程逻辑器件cpld与单片机双向通信的源程序
可编程逻辑器件cpld与单片机双向通信的源程序-Programmable logic device CPLD and MCU for two-way communication of the source
- 2022-01-25 20:21:15下载
- 积分：1
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Huffman_enc_dec
Huffman encoder decoder verilog
- 2021-03-21 00:49:17下载
- 积分：1
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eda
EDA 正弦信号发生器：正弦信号发生器的结构有四部分组成，如图1所示。20MHZ经锁相环PLL20输出一路倍频的32MHZ片内时钟,16位计数器或分频器CNT6，6位计数器或地址发生器CN6，正弦波数据存储器data_rom。另外还需D/A0832（图中未画出）将数字信号转化为模拟信号。此设计中利用锁相环PLL20输入频率为20MHZ的时钟，输出一路分频的频率为32MHZ的片内时钟，与直接来自外部的时钟相比，这种片内时钟可以减少时钟延时和时钟变形，以减少片外干扰 还可以改善时钟的建立时间和保持时间，是系统稳定工作的保证。CNT6用来将32MHZ进行8分频得到4096HZ的频率提供给CN6与data_rom时钟信号。由CLK端输入20MHZ的时钟信号，在DOUT端就可输出稳定的正弦信号。(Sine signal generator has the structure of four parts, as shown in figure 1 below. The 20 MHZ phase lock loop PLL20 output all the way of frequency doubled within 32 MHZ slice clock, 16 counter or prescaler CNT6, six counter or address generator CN6, sine data storage data_rom. In addition to D/A0832 (shown in not draw) will digital signal into analog signals. This design using the phase lock loop PLL20 input frequency for 20 MHZ clock, the output of the frequency of all points frequency of 32 pieces (MHZ clock, and comes directly from the external clock, compared to this piece of clock can reduce the clock in delay and clock deformation, to reduce the interference of Can also improve the establishment of the clock time and keep time, is the system stability of assurance. CNT6 used to will and to 8 MHZ get 4096 HZ dividing the frequency to provide CN6 and data_rom clock signal. The input by CLK 20 MHZ clock signal, in DOUT end can output stable sine signals.
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- 2021-03-07 15:49:29下载
- 积分：1
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cpld 控制 8
cpld 控制 8-32M sdram 控制器 maxII epm570实现。-CPLD control 8-32M sdram controller maxII epm570 realize.
- 2022-02-20 19:59:10下载
- 积分：1
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SR_DDS
DDS信号源设计，有正弦波，方波，三角波，AM波，FM波，还有PSK,FSK,16QAM等多种信号产生。(DDS signal source design, there are sine, square wave, triangle wave, AM wave, FM wave, as well as PSK, FSK, 16QAM and other signal generation.)
- 2016-03-20 22:04:51下载
- 积分：1
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这是用VHDL编写的FPGA与计算机进行串口通信的程序和一个LED程序...
这是用VHDL编写的FPGA与计算机进行串口通信的程序和一个LED程序-VHDL and FPGA prepared by the computer serial communication procedures and an LED procedures
- 2022-01-25 15:54:47下载
- 积分：1
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5.7
设计一个简单的FIR滤波器，并按要求确定滤波器的系统函数。(Design a simple FIR filter, and determine the filter according to the requirement of system function.)
- 2015-04-17 18:26:49下载
- 积分：1
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这是个vhdl编写的16bit的加减法器
这是个vhdl编写的16bit的加减法器-This is vhdl prepared by the modified instruments used in the 16bit
- 2022-02-15 07:17:54下载
- 积分：1
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2
说明： ADV7179芯片的驱动程序，基于FPGA硬件实现，已经验证可以使用(ADV7179 chip drivers, FPGA-based hardware implementation has been verified using)
- 2011-02-21 16:06:56下载
- 积分：1
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Y312448.zip
基于VHDL的SDH专用芯片的TOP-DOWN设计，
内有全套源码以及图片，内容详尽，绝对真实可靠！(VHDL based on the SDH ASIC Design TOP-DOWN, which has a full set of source code, as well as pictures, and detailed, reliable and absolutely true!)
- 2008-05-12 19:21:03下载
- 积分：1
