-
list_ch06_02_debounce
Eliminate the program of key bounce
- 2012-12-23 00:22:42下载
- 积分：1
-
用于FPGA的反Z变换算法的Verilog代码。可用于JPEG及MPEG压缩算法。...
用于FPGA的反Z变换算法的Verilog代码。可用于JPEG及MPEG压缩算法。-FPGA for the anti-Z transform algorithm of Verilog code. Can be used in JPEG and MPEG compression algorithms.
- 2022-02-25 16:18:57下载
- 积分：1
-
freeDev数字应用开发板中的VGA控制器的IP核的verilog实现
freeDev数字应用开发板中的VGA控制器的IP核的verilog实现-freeDev digital application development board of the VGA controller IP core implementation of the verilog
- 2022-03-01 11:34:28下载
- 积分：1
-
dp_xiliux the CPLD Verilog design experiments, 7 LED demo. code test.
dp_xiliux 的 CPLD Verilog设计实验,7个LED演示.代码测试通过. -dp_xiliux the CPLD Verilog design experiments, 7 LED demo. code test.
- 2023-03-22 17:40:04下载
- 积分：1
-
LFM
该程序使用Verilog语言产生LFM信号(The program uses Verilog language to generate LFM signals.)
- 2021-04-19 09:38:51下载
- 积分：1
-
本实施multilplier在vhdl.this源代码是有用的电脑学习…
this implemented multilplier in vhdl.this source code is useful for computer student and hardware engineering.-this is implemented multilplier in vhdl.this source code is useful for computer student and hardware engineering.
- 2022-01-31 00:27:28下载
- 积分：1
-
Booth乘法器
- 2022-10-22 10:30:04下载
- 积分：1
-
example
一个电子秒表，最大显示59.99,具有暂停和reset功能(An electronic stopwatch, the maximum display 59.99, with a pause and reset functions)
- 2013-12-17 12:28:14下载
- 积分：1
-
ask调制，基于VHDL仿真平台，解调同样给出，此程序经过验证
ask调制，基于VHDL仿真平台，解调同样给出，此程序经过验证-ask modulation, based on VHDL simulation platform, demodulator is the same, this procedure proven
- 2022-02-07 06:59:29下载
- 积分：1
-
3-8
3-8译码器，可以讲三位二进制输入转换为8中取1的输出信号(3-8 decoder, you can talk about the three binary input is converted to 8 of the output signal from 1)
- 2009-07-16 17:23:30下载
- 积分：1
