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正弦波在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过...
正弦波在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-sine wave in dspbuilder under VHDL source code and test incentives document matl ab model, the simulation under through modelsim
- 2023-07-26 10:55:02下载
- 积分:1
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My_POC
Simulating the functions of POC.(Simulating the functions of POC. In VHDL, with ISE.)
- 2017-09-12 15:12:32下载
- 积分:1
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ddr3_test
说明: 通过循环读写DDR3内存,了解其工作原理和DDR3控制器的写法,由于DDR3控制复杂,控制器的编写难度高,这里笔者介绍XILINX的MIG控制器情况下应用,是后续音频、视频等需要用到SDRAM实验的基础。(Through reading and writing DDR3 memory circularly, we can understand its working principle and the writing method of DDR3 controller. Because of the complexity of DDR3 control, it is difficult to write the controller. Here, the author introduces the application of Xilinx's MIG controller, which is the basis of SDRAM experiment for subsequent audio and video.)
- 2021-04-16 10:00:15下载
- 积分:1
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LDPC码的消息节点(Bitnode)消息更新过程的VHDL语言实现
LDPC码的消息节点(Bitnode)消息更新过程的VHDL语言实现-LDPC code of the message node (Bitnode) news update process of the VHDL language
- 2022-12-16 00:40:03下载
- 积分:1
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VHDL硬件描述语言与数字逻辑电路设计
VHDL硬件描述语言与数字逻辑电路设计-VHDL hardware description language and digital logic circuit design
- 2023-03-10 23:05:04下载
- 积分:1
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VHDLgoldbook
VHDL黄金参考手册,能让你更好的学习了解VHDL语言(VHDL gold reference manual, can make you a better learn VHDL language)
- 2013-12-05 16:06:19下载
- 积分:1
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CPU
C++获取CPU占用率,一个类和一个头文件(Gets the CPU Use rate)
- 2015-01-23 11:15:32下载
- 积分:1
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sin and cos with cordic VHDL
该模块采用cordic算法计算正弦和余弦,并采用参数化方式实现。 ;包中存在其他模块。
- 2022-05-25 06:14:20下载
- 积分:1
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ask调制,基于VHDL仿真平台,解调同样给出,此程序经过验证
ask调制,基于VHDL仿真平台,解调同样给出,此程序经过验证-ask modulation, based on VHDL simulation platform, demodulator is the same, this procedure proven
- 2022-02-07 06:59:29下载
- 积分:1
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FPGA VERILOG 用DCFIFO实现 跨时钟域的数据传输,已验证,直接可用...
FPGA VERILOG 用DCFIFO实现 跨时钟域的数据传输,已验证,直接可用-FPGA VERILOG using DCFIFO realize cross-clock domain data transfer, has been verified, directly available
- 2022-04-17 14:15:55下载
- 积分:1