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fifo
说明: 用FPGA完成256*8的存储器的读写操作( complete reading and writing 256* 8 memory with FPGA )
- 2010-04-24 17:07:06下载
- 积分:1
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本代码介绍了使用VHDL开发FPGA的一般流程,最终采用了一种基于FPGA的数字频率的实现方法。该设计采用硬件描述语言VHDL,在软件开发平台ISE上完成,可以...
本代码介绍了使用VHDL开发FPGA的一般流程,最终采用了一种基于FPGA的数字频率的实现方法。该设计采用硬件描述语言VHDL,在软件开发平台ISE上完成,可以在较高速时钟频率(100MHz)下正常工作。该设计的频率计能准确的测量频率在1Hz到100MHz之间的信号。使用ModelSim仿真软件对VHDL程序做了仿真,并完成了综合布局布线,最终下载到芯片Spartan-II上取得良好测试效果。-the code on the FPGA using VHDL development of the general process, finally adopted a FPGA-based digital frequency method. The design using VHDL hardware description language, the software development platform ISE completed, the higher speed clock frequency (100MHz) under normal work. The design of the frequency meter can be accurately measured in a frequency of 100MHz between Hz signal. Use ModelSim VHDL simulation software to do the simulation process, and completed a comprehensive layout cabling, downloaded to the final chip Spartan-II made good on the test results.
- 2022-10-09 05:15:03下载
- 积分:1
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遥控器接收解码电路
设计遥控器接收解码电路。该电路接收编码后的串行数据,解码输出数据。电路接收
到的串行数据的格式为: 4 位同步码“ 1010”, 4 位数据(高位在前), 1 位奇校验码(对前 8 位数据校验)(Design of remote control receiver decoding circuit. The circuit receives the encoded serial data and decodes the output data. The format of the serial data received by the circuit is: 4 bit synchronous code "1010", 4 bit data (high in the front), 1 bit parity check code (check for the first 8 bits of data))
- 2017-11-27 15:10:34下载
- 积分:1
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SHA256
SHA256加密过程,非常详细,内附原码,还有文档,很可用~(SHA256 encryption process, very detailed, containing the original code, as well as documents, it is available ~)
- 2020-11-25 16:19:33下载
- 积分:1
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Xilinx FPGA RAM块可通过JTAG
Xilinx FPGA block RAM reconfig via JTAG
- 2022-01-25 19:09:13下载
- 积分:1
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I2C 串口通讯Xilinx项目源码
拷贝到硬盘,用ISE打开工程文件即可。...
I2C 串口通讯Xilinx项目源码
拷贝到硬盘,用ISE打开工程文件即可。-I2C Serial Communication Xilinx source project are copied to the hard drive, using ISE project file can be opened.
- 2022-02-20 02:20:00下载
- 积分:1
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FPGA simulation examples, Verilog coding, the process in detail, code easy to un...
FPGA的仿真实例,Verilog代码编写,过程详尽,代码易懂。第二个文档-FPGA simulation examples, Verilog coding, the process in detail, code easy to understand. The second document
- 2022-05-04 23:56:16下载
- 积分:1
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8位相等比较器,比较8位数是否相等
8位相等比较器,比较8位数是否相等
-- 8-bit Identity Comparator
-- uses 1993 std VHDL
-- download from www.pld.com.cn & www.fpga.com.cn-eight other phase comparators, Comparing the same whether the median 8-- 8-bit Identity Comparator-- uses 1993 std VHDL-- download from www.pld.com.cn
- 2022-06-21 10:57:15下载
- 积分:1
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hdb3_v3
Quartus环境下使用Verilog编写的HDB3编解码程序,RTL和时序仿真已过(Quartus under the environment of a HDB3 protocol procedures written in Verilog, RTL and timing simulation has be passed)
- 2015-11-24 21:56:05下载
- 积分:1
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FPGA控制AD7321的模块
FPGA控制AD7321的模块,是本人亲自试验过的。有Verilog源码,和简单文档(Fpga control module of ad 7321, is I personally tested. Verilog source code, and simple documentation)
- 2018-01-31 20:04:27下载
- 积分:1