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FPGA控制AD7321的模块

于 2018-01-31 发布文件大小:1934KB

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代码说明：

FPGA控制AD7321的模块，是本人亲自试验过的。有Verilog源码，和简单文档(Fpga control module of ad 7321, is I personally tested. Verilog source code, and simple documentation)

文件列表：

AD\Addr_Generator.v, 2076 , 2009-07-29
AD\Addr_Generator.v.bak, 2073 , 2009-07-26
AD\ADS2807_Ctrl.v, 2780 , 2009-07-29
AD\ADS2807_Ctrl.v.bak, 2776 , 2009-07-29
AD\ADS2807控制.docx, 822524 , 2009-07-28
AD\ADS2807控制.pdf, 1022560 , 2009-07-28
AD\div_N.v, 2845 , 2009-07-28
AD\div_N.v.bak, 1406 , 2009-07-26
AD\截图\ADS2807时序图.jpg, 32155 , 2009-07-26
AD\截图\AD控制单元ROM控制字.jpg, 14690 , 2009-07-28
AD\截图\AD控制单元仿真模块.jpg, 141742 , 2009-07-28
AD\截图\AD控制单元仿真波形.jpg, 78823 , 2009-07-28
AD\截图\分频器仿真模块.jpg, 49039 , 2009-07-28
AD\截图\分频器仿真波形.jpg, 31826 , 2009-07-28
AD\截图\地址发生器仿真模块.jpg, 62451 , 2009-07-28
AD\截图\地址发生器仿真波形.jpg, 42035 , 2009-07-28
AD\截图\控制框图.vsd, 65024 , 2009-07-26
AD\截图\系统仿真模块.jpg, 175512 , 2009-07-28
AD\截图\系统仿真波形.jpg, 141772 , 2009-07-28
AD\截图, 0 , 2009-07-28
AD, 0 , 2009-07-29

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