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half_band
半带滤波器verilog源代码，主要用于采样率变换系统中，采用乘法积累加器，很好的例子，供大家参考(Half band filter verilog code, mainly for the sampling rate conversion system, use the multiplication accumulation adder, a good example, for your reference)
- 2020-12-23 10:59:07下载
- 积分：1
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v5_emac
以太网的FPGA程序实现以太网的FPGA程序实现以太网的FPGA程序实现(enternet verilog fpga)
- 2013-12-15 23:08:11下载
- 积分：1
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信号的提取
说明： 1、SignalTap II Logic Analyzer使用方法；
2、掌握捕获条件的设置
3、学会硬件信号分析，了解硬件信号监视和软件调试的差异(1. How to use signaltap II logic analyzer;
2. Master the setting of capture conditions
3. Learn hardware signal analysis, understand the difference between hardware signal monitoring and software debugging)
- 2021-01-11 14:31:37下载
- 积分：1
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Verilog HDL编写的CPU模型，很经典，比较通用
Verilog HDL编写的CPU模型，很经典，比较通用-Verilog HDL prepared by the CPU model, classic, more generic
- 2022-03-21 08:58:27下载
- 积分：1
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jk-filpflop
这个是vhdl中很常见的jk filpflop的文件只用于很小数位的变化 其中的jk文件是up down运算都符合的(This is a very common vhdl jk filpflop file is only used for very small changes in a digital file which jk is up down operations are met)
- 2013-11-19 11:43:07下载
- 积分：1
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truck_lights
Lights, Car light emulator for turn, stop and emergency
- 2012-11-06 18:27:06下载
- 积分：1
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Dec_mul
时间同步后即可确定每帧数据的起始位置，这样就能完整的截取下每一帧。但是，数据中还带有频偏信息。在常规的通信系统中，多普勒很小仅仅会带来很小的频偏，但是在大多普勒的情况下，频偏将非常大，20马赫的速度将会带来将近34K的频偏。因此，如何很好的纠正频偏即为本系统的难点。
OFDM中，我们将大于子载波间隔倍数的频偏称为整数倍频偏，而将小于一个子载波间隔的频偏称为小数倍频偏。频偏矫正精度只要能保证小于十分之一倍的子载波间隔，频偏就不会对均衡和解调造成影响。本文中我们借鉴这种思想，由于硬件资源限制，我们将在接收端做64点FFT，即相当于将频域划分为64份，我们将小于 的频偏称为小数倍频偏，将 整数倍的频偏称为整数倍频偏。本程序即基于SCHIMDL经典方法完成小数倍频偏纠正(After time synchronization can determine the starting position of each frame data, so you can complete the interception of each frame. However, in the data with frequency information. In conventional communication systems, doppler small will bring only small deviation, but in the case of most of the doppler, frequency PianJiang is very large, 20 Mach speed will lead to deviation of nearly 34 k. Therefore, how to good to correct deviation is the difficulty of this system.
OFDM, we will be bigger than the sub-carrier spacing ratio of frequency deviation is called the integer frequency offset, and the interval will be less than a child carrier frequency offset is called decimal frequency doubling. Deviation is less than one over ten times as long as can guarantee accuracy of sub-carrier spacing, deviation will not affect balance and demodulation. This article, we draw lessons from the idea, due to the limited hardware resources, we will do 64 points FFT at the receiving end, which is equ)
- 2013-12-26 18:00:24下载
- 积分：1
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1．初始状态为4个方向的红灯全亮，时间1秒。
2．东、西方向绿灯亮，南、北方向红灯亮。东、西方向通车，时间30秒。
3．东、西方向黄灯闪烁，南、北方...
1．初始状态为4个方向的红灯全亮，时间1秒。
2．东、西方向绿灯亮，南、北方向红灯亮。东、西方向通车，时间30秒。
3．东、西方向黄灯闪烁，南、北方向红灯亮。时间2秒。
4．东、西方向红灯亮，南、北方向绿灯亮。南、北方向通车，时间15秒。
5．东、西方向红灯亮，南、北方向黄灯闪烁。时间2秒。
6．返回2，继续运行。
-1. Initial state for four whole direction of the red lights lit up, a second time. 2. East and West to the green, in the south, north to the red light. West and the East to open in time for 30 seconds. 3. East and West to the blinking yellow light, in the south, north to the red light. Time 2 seconds. 4. East and West to the red light, in the south, north to the green. South and North to the opening time of 15 seconds. 5. East and West to the red light, in the south, north to the flashing yellow light. Time 2 seconds. 6. Return 2, continued to operate.
- 2023-01-12 03:20:04下载
- 积分：1
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CDCM6208_SPI
说明： 完成对cdcm6208的时钟芯片的配置，输出高频时钟(cdcm6208 cofigure using SPI interface)
- 2021-02-06 18:29:56下载
- 积分：1
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latticeECP3-serdes-test-code
lattice ECP3系列高速FPGA serdes测试代码(lattice ECP3 series high speed serdes test code)
- 2021-03-25 01:39:14下载
- 积分：1
