登录
首页 » VHDL » Verilog 下 16位除法算法程序,高精度,固定17个时钟周期

Verilog 下 16位除法算法程序,高精度,固定17个时钟周期

于 2022-01-27 发布 文件大小:142.80 kB
0 61
下载积分: 2 下载次数: 1

代码说明:

Verilog 下 16位除法算法程序,高精度,固定17个时钟周期-Verilog under 16 division algorithm procedures, high-precision, fixed in 17 clock cycles

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • CAM
    Content-addressable memory (CAM) is a special type of computer memory used in certain very-high-speed searching applications. It is also known as associative memory, associative storage, or associative array, although the last term is more often used for a programming data structure.
    2014-12-06 00:33:45下载
    积分:1
  • LFM
    该程序使用Verilog语言产生LFM信号(The program uses Verilog language to generate LFM signals.)
    2021-04-19 09:38:51下载
    积分:1
  • 用于FPGA的反量化算法的HDL编码,包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。...
    用于FPGA的反量化算法的HDL编码,包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。-FPGA used to quantify anti-HDL coding algorithms, including VHDL and Verilog code. Can be used in JPEG and MPEG compression algorithms.
    2022-04-08 04:33:51下载
    积分:1
  • jk-filpflop
    这个是vhdl中很常见的jk filpflop的文件只用于很小数位的变化 其中的jk文件是up down运算都符合的(This is a very common vhdl jk filpflop file is only used for very small changes in a digital file which jk is up down operations are met)
    2013-11-19 11:43:07下载
    积分:1
  • This is a use of the VHDL language Parallel to Serial procedures, In altera deve...
    这是一个用VHDL语言编写的并口转串口程序,在altera开发系统下验证通过,运用于开发板与计算机之间的通信,源程序可以提供参考-This is a use of the VHDL language Parallel to Serial procedures, In altera development system under test passed, the development of applied between the panels and computer communications, can provide a reference source
    2022-03-23 13:41:19下载
    积分:1
  • FPGA-based--DC-speed-controller
    针对某船舶模型定位系统中调速电机,以FPGA(现场可编程门阵列)为控制器,采用数字比例积分调节器实现电机的速度控制算法,设计出数字化调速控制器(Positioning system for a ship model in the motor speed, the FPGA (field programmable gate array) for the controllers, proportional integral regulator with digital speed of the motor control algorithm, designed digital speed controller)
    2011-05-17 15:50:57下载
    积分:1
  • MIPS处理器的组员大作业,可以直接运行,提交,环境是quartus
    MIPS处理器的组员大作业,可以直接运行,提交,环境是quartus-MIPS processor crew great job, you can run directly, the author, the environment is quartusII
    2023-05-21 22:20:04下载
    积分:1
  • these files are written in verilog but i am uploading in text format
    these files are written in verilog but i am uploading in text format
    2022-08-19 04:15:42下载
    积分:1
  • sdram_control
    SDRAM控制器 带仿真模型文件 仿真通过(Simulation model file simulation through SDRAM controller)
    2017-12-07 10:54:24下载
    积分:1
  • second7-02
    在quartusII环境下采用对编解码芯片HD6408和HD6409驱动的方式实现曼彻斯特编解码(Environment in quartusII codec chip used on the HD6408 and HD6409-driven way to achieve encoding and decoding of Manchester)
    2020-11-02 10:19:53下载
    积分:1
  • 696518资源总数
  • 104298会员总数
  • 46今日下载