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Verilog代码支持IO中断的CPU实现
Verilog代码,支持IO,中断的cpu实现。(Verilog code, support IO, interrupt cpu implementation.)
- 2020-07-05 20:28:59下载
- 积分:1
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turbo_dinter
说明: 电网协议信道解交织器设计FPGA实现,适用于PB16的宽带电力线载波通信(Grid protocol channel deinterleaver design FPGA implementation, suitable for PB16 broadband power line carrier communication)
- 2020-05-08 15:53:18下载
- 积分:1
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Digital signal source, the output of different frequency, phase is the cosine si...
数字信号源,输出不同频率,相位的正余弦信号,-Digital signal source, the output of different frequency, phase is the cosine signal,
- 2022-04-23 09:40:37下载
- 积分:1
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dds_test
说明: 直接数字式频率合成器DDS设计、Verilog。
产生的信号可以是正弦波或方波、三角波、锯齿波等,自选。
采用DDS技术,将所需生成的波形写入ROM中,按照相位累加原理合成任意波形。
此方案得到的波形稳定,精度高,产生波形频率范围大,容易产生高频。
本实验在设计的模块中,包含以下功能:
(1)通过 freq 信号输入需要的频率的值;
(2)通过 wave_sel 信号选择所需的波形;
(3)通过 amp_adj 信号选择波形放大的倍数。(DDS design of direct digital frequency synthesizer, Verilog.
The generated signal can be sinusoidal or square wave, triangular wave, sawtooth wave and so on, optional.
By using DDS technology, the required waveforms are written into ROM, and arbitrary waveforms are synthesized according to the principle of phase accumulation.
The waveform obtained by this scheme is stable, accurate and easy to generate high frequency waveform.
This experiment includes the following functions in the designed module:
(1) Input the required frequency value through freq signal;
(2) Choosing the required waveform by wave_sel signal;
(3) Select the multiplier of waveform amplification by amp_adj signal.)
- 2019-01-19 16:07:50下载
- 积分:1
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flash
本程序是fpga控制flash的读写程序,包括了程序和仿真时的测试文件(fpga flash)
- 2013-07-21 14:47:36下载
- 积分:1
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这是一个时钟的VHDL源代码,其中包含了源代码,以及工程。
这是一个时钟的VHDL的源程序,里面包含有源程序,还有工程文件对大家很有帮助-This is a clock VHDL source code, which contains the source code, as well as engineering documents helpful to everyone
- 2023-03-26 14:20:04下载
- 积分:1
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Can realize the time digital clock display, and on the hours, minutes, seconds t...
能实现数字钟中时间的显示,并可对小时,分钟,秒进行调整-Can realize the time digital clock display, and on the hours, minutes, seconds to adjust
- 2022-04-29 18:33:18下载
- 积分:1
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verilog
关于USB开发的verilog开发程序,非常的全面,学习FPGA开发时用得着。(About USB development verilog development process, very comprehensive, learning FPGA development time worthwhile.)
- 2013-12-26 18:29:35下载
- 积分:1
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QPSK
说明: 基于FPGA的QPSK调制解调电路设计与实现 (QPSK)
- 2010-04-07 14:15:21下载
- 积分:1
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baseband_verilog
verilog实现的基带信号编码,整个系统分为六个模块,分别为:时钟模块,待发射模块,卷积模块,扩频模块,极性变换和内插模块,成型滤波器(verilog implementation baseband signal coding, the entire system is divided into six modules, namely: the clock module, to be launched modules, convolution module, spread spectrum modules, polarity transform and interpolation modules, forming filter)
- 2009-10-08 10:19:34下载
- 积分:1