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放大內建圖片
应用背景
背景是DE2-70的板子,使用vga線,再用開關作為放大按鈕
sw3放大按鈕
sw2控制垂直水平放大
sw1控制放大2倍或4倍
需接上vga使用螢幕輸出
关键技术
技術的部份,vga的輸出一個,分為水平為字垂直位置掃描,之後還有圖檔的輸出
圖檔分為三原色,共8個顏色輸出
不過本例的重點為放大,控制其DELTA便可以控制圖片的大小
控制鈕為在板子上的SWITH
- 2023-01-31 22:40:04下载
- 积分:1
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iic
iic 总线 verilog 源代码
标准i2c总线, 有sda scl 时钟,频率自定(IIC bus standard Verilog source code i2c bus, has sda scl clock, the frequency of self-)
- 2007-10-24 17:52:33下载
- 积分:1
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FPGA 64位除法器 verilog
用verilog语言实现的除法器,实现方式为移位减
- 2023-09-02 08:35:03下载
- 积分:1
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Xilinx-Timing
Xilinx FPGA 时序约束资料,原厂出品,经典不需要理由(Xilinx FPGA timing constraint information, original, classic no reason)
- 2013-05-17 09:31:26下载
- 积分:1
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FPGA
verilog编写的QPSK发射机的FPGA部分,已经过验证,完全达到要求。调制矢量误差4%(QPSK transmitter verilog prepared by the FPGA portion, has been proven, fully meet the requirements. Modulation vector error of 4 )
- 2013-10-08 14:58:23下载
- 积分:1
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SystemOfTaxiFeeBasedOnVerilogHDL
摘 要:以上海地区的出租车计费器为例,利用Verilog HDL语言设计了出租车计费器,使其具有时间
显示、计费以及模拟出租车启动、停止、复位等功能,并设置了动态扫描电路显示车费和对应时间,显示
了硬件描述语言Verilog—HDL设计数字逻辑电路的优越性。源程序经MAX+PLUS Ⅱ软件调试、优
化,下载到EPF1OK10TC144—3芯片中,可应用于实际的出租车收费系统。
关键词:Verilog HDL;电子自动化设计;硬件描述语言;MAX+PLUSⅡ(Abstract: Shanghai taxi meter as an example, the use of Verilog HDL language designed taxi meter so that it will have the time display, billing, as well as analog taxis to start, stop, reset and other functions, and set up a dynamic scanning circuit shows that the fare and the corresponding time, shows the hardware description language Verilog-HDL design of the superiority of digital logic circuits. Source by MAX+ PLUS Ⅱ software debugging, optimization, downloaded to EPF1OK10TC144-3 chip, can be applied to the actual taxi fare collection system. Keywords: Verilog HDL electronic design automation hardware description language MAX+ PLUS Ⅱ)
- 2007-09-11 10:52:52下载
- 积分:1
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SVPWM-VHDL
fpga永磁同步电机矢量控制系统,包括死区等模块(fpga foc)
- 2016-06-13 19:53:32下载
- 积分:1
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CLZ_32bit
前导零的计算 (Calculation of leading zeros)
- 2021-03-31 21:29:09下载
- 积分:1
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FloatPoint Arithmetic
Float Point Add, Multiply, and Divide arithmetic. You can change and modify the add block and reuse it in FPGA or ASIC chip. The running clock is dependent of the technology you used in the ASIC.
- 2022-06-13 03:38:57下载
- 积分:1
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灰色计数器
资源描述这是一个verilog代码转换成二进制码格雷码,这有助于减少开关活动从而功率降低。
- 2023-03-03 23:45:04下载
- 积分:1