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FPGA-design-and-application
已经正式出版,西安电子科技大学出版社,FPGA设计及应用,作者褚振勇(Has been officially published, Xi' an University of Electronic Science and Technology Publishing House, FPGA design and application, the author Zhezhengyong)
- 2009-06-03 15:57:31下载
- 积分:1
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FPGA development board to write the Verilog code: function is from the client co...
FPGA开发板上写的Verilog代码:
功能是从电脑端发送一个字节,然后把它接收回来。
-FPGA development board to write the Verilog code: function is from the client computer sends a byte, and then receive it back.
- 2022-03-17 03:39:34下载
- 积分:1
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jk-filpflop
这个是vhdl中很常见的jk filpflop的文件只用于很小数位的变化 其中的jk文件是up down运算都符合的(This is a very common vhdl jk filpflop file is only used for very small changes in a digital file which jk is up down operations are met)
- 2013-11-19 11:43:07下载
- 积分:1
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bundle_test5
说明: 一个具备bp协议典型功能的数据传输系统(超时重传机制以及托管传输)包含五个节点(A data transmission system with typical functions of BP protocol (Overtime retransmission mechanism and managed transmission) consists of five nodes)
- 2019-12-02 19:06:44下载
- 积分:1
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uart_byte_rx
libero soc工程,实现通过串口接收到单字节数据后并返回发送给上位机(Libero SOC project, which realizes receiving single byte data through serial port and sending it back to host computer)
- 2020-06-21 09:20:01下载
- 积分:1
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divisor
Time divisor vhdl code
- 2009-06-02 21:31:05下载
- 积分:1
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一个双向总线的vhdl实现
一个双向总线的vhdl实现-a two-way bus VHDL achieve
- 2023-07-29 00:40:02下载
- 积分:1
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sph-original-codes
SPH的原始代码,希望可以帮到大家啊关于模拟poiseuille的(simulate poiseuille fuild)
- 2020-10-22 10:27:23下载
- 积分:1
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crc16CCITT
自己用verilog编写的crc16-ccitt码的产生,是并行的。(Crc16-ccitt code written in verilog generate parallel.)
- 2012-12-13 09:46:58下载
- 积分:1
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project_first
说明: basys3的数字钟,可以显示00.00-59.59(Digital clock of basys3,It can display 00.00-59.59)
- 2019-06-18 10:37:53下载
- 积分:1