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这是一个数字时钟数字逻辑电路，整个工程包上传…
这是一个数字时钟的数字逻辑电路，整个工程打包上传，时钟可以计时、校时、整点报时、定时闹钟。使用电路图实现的。在quatarsII里面仿真的并且下载到DE2板上运行过。-This is a digital clock digital logic circuits, the whole project package upload, the clock could be time, school hours, the whole point timekeeping, timing alarm clock. The use of circuit implementation. The quatarsII inside the simulation, and downloaded to the DE2 board to run-off.
- 2022-08-06 10:22:24下载
- 积分：1
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SoC_WishboneSystem
SoC-Wishbone System IP核的VHDL语言源代码，需要的开发环境是QUARTUS II 6.0。(SoC-Wishbone System IP core VHDL language source code, the need for the development environment is QUARTUS II 6.0.)
- 2008-01-03 11:14:59下载
- 积分：1
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汽车尾灯控制系统
汽车尾灯控制器的VHDL程序实现
汽车尾灯控制系统
汽车尾灯控制器的VHDL程序实现
-car taillight control system controller car taillight VHDL program
- 2022-11-01 18:00:03下载
- 积分：1
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能够实现8位的无符号数的乘除法，模拟了笔算的过程
- 2022-12-11 10:00:03下载
- 积分：1
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oc_i2c_master_top_v92
I2C IP for Quartus V9.0 sp2, can used in SOPC builder.
- 2009-10-10 10:43:18下载
- 积分：1
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jiaotongdeng
运用VHDL语言编写的交通灯实现程序,能模拟十字路口的交通灯控制(VHDL language using traffic lights to achieve program can simulate the traffic light controlled crossroads)
- 2011-06-06 16:26:55下载
- 积分：1
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frequence1
基于FPGA的等精度数字频率计，包含FPGA和单片机通信程序，解释非常详细。经过调试成功。(FPGA-based Precision Digital frequency meter, including FPGA and MCU communication program, explained in great detail. After successful commissioning.)
- 2020-10-30 20:29:56下载
- 积分：1
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RS_255_223_ENCODER
rs255编码解码器，verilog描述，FPGA实现(RS255 223 ENCODER)
- 2015-03-30 09:52:09下载
- 积分：1
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ask调制，基于VHDL仿真平台，解调同样给出，此程序经过验证
ask调制，基于VHDL仿真平台，解调同样给出，此程序经过验证-ask modulation, based on VHDL simulation platform, demodulator is the same, this procedure proven
- 2022-02-07 06:59:29下载
- 积分：1
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ytupn
Very suitable for the study using computer vision, Analysis of the signal time domain, frequency domain, cepstrum, cyclic spectrum, etc. The performance of the program has reached a high level.
- 2017-09-02 18:07:13下载
- 积分：1
