-
fpga_coder_module
本人编写的FPGA光电编码器输入模块,没有实验,但仿真基本实现,希望有参考价值.(FPGA optical encoder input module, there is no experimental, but simulation technology, hope to have reference value.)
- 2021-04-21 01:58:50下载
- 积分：1
-
091655
基于fpga的coms摄像头
扫描，参考文献，(Fpga based on the coms camera scan, reference literature,)
- 2010-08-09 01:03:12下载
- 积分：1
-
freq
vhdl八位十进制数字频率计的设计，顶层和数码管扫描模块(vhdl eight decimal digital frequency meter design, top-level and digital tube scanning module)
- 2012-10-09 15:09:22下载
- 积分：1
-
costas
costas的verilog程序，包含乘法器，DDS，鉴相器，环路滤波器等模块(costas the verilog program, including multipliers, DDS, phase detector, loop filter modules)
- 2011-08-19 10:20:53下载
- 积分：1
-
canbus verilog实现，原代码文件
canbus verilog实现，原代码文件-canbus verilog implementation, the original source document
- 2022-06-15 18:20:23下载
- 积分：1
-
bit7_Binary_to_BCD_LED
二进制转十进制BCD码 Verilog语言 quartusII(Binary to decimal BCD code Verilog language quartusII)
- 2013-09-14 16:49:39下载
- 积分：1
-
modelsim设计的可调占空比的方波程式
modelsim设计的可调占空比的方波程式-modelsim designed adjustable duty cycle of the square wave program
- 2022-09-02 05:05:03下载
- 积分：1
-
jitter_eliminate
verilog描述的实用消抖电路，采用三个D触发器和一个JK触发器。使用emacs编写源文件，iverilog仿真通过，内有png仿真图像截屏(verilog description of the practical elimination shake circuit, using three D flip-flop and a JK flip-flop. Prepared source files using the emacs , iverilog simulation adopted, within the simulation images png screenshots)
- 2009-11-24 15:51:44下载
- 积分：1
-
索FPGA Verilog使用ROM和RAM实现高dcfifo
alteral FPGA VERILOG 利用 ROM DCFIFO 和RAM
实现高速到低速时钟域的数据传输 ，值得学习。-alteral FPGA VERILOG using ROM DCFIFO and RAM to realize high-speed low-speed clock domain data transfer, it is worth learning.
- 2023-05-06 14:25:03下载
- 积分：1
-
通信协议AHB_LITE
AHB_Lite 通信协议的FPGA Verilog 设计(AHB_Lite communication protocol Verilog design in FPGA)
- 2020-12-15 10:09:14下载
- 积分：1
