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数字相位
PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上；顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), Fo (Q5) is the local output frequency. Objective is to extract data input clock signal (Q5), its frequency and data rate line, the clock rising edge of the lock data the rising and falling edge; top-level document is PLL.GDF
- 2023-05-28 08:00:03下载
- 积分：1
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code
浙江大学体系结构实验代码 实现流水线的forwarding(Architecture, Zhejiang University Experimental code pipeline forwarding)
- 2020-09-26 11:57:46下载
- 积分：1
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可控制器
应用背景此代码是用于执行器和传感器，可以在网络中实现一个很好的连接与其他节点和主。关键技术VHDL代码 ；可以控制位CRC校验和填料-掩模的验收规范
- 2022-01-26 00:30:01下载
- 积分：1
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HDMI接口编解码传输模块ASIC设计_刘文杰
? 熟悉IIC协议总线协议，采用IIC总线对图像采集传感器寄存器进行配置，并转换为RGB565格式。
? 利用异步FIFO完成从摄像头输出端到SDRAM 和SDRAM 到VGA 接口各跨时钟域信号的传输和处理。
? 利用 SDRAM 接口模块的设计，实现了刷新、读写等操作；为提高SDRAM 的读写带宽，均采用突发连续读写数据方式；并采用乒乓操作实现 CMOS 摄像头与VGA的帧率匹配。
? 利用双线性插值方法实现对图像640×480到1024×768的放大操作。
? 完成VGA显示接口设计。(Familiar with IIC protocol bus protocol, IIC bus is used to configure the register of image acquisition sensor and convert it into RGB565 format.
Asynchronous FIFO is used to transmit and process signals across clock domain from camera output to SDRAM and SDRAM to VGA interface.
With the design of SDRAM interface module, refresh, read and write operations are realized. In order to improve the read and write bandwidth of SDRAM, burst continuous read and write data mode is adopted, and table tennis operation is used to achieve frame rate matching between CMOS camera and VGA.
The bilinear interpolation method is used to enlarge the image from 640*480 to 1024*768.
Complete the VGA display interface design.)
- 2020-06-25 04:00:02下载
- 积分：1
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FPGA
基于fpga的多功能电子钟的设计非常使用希望对大家有帮助啊-FPGA-based multi-functional electronic clock design to use would like to help everyone ah
- 2023-06-23 00:15:03下载
- 积分：1
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VHDL-development
VHDL入门级好教材《VHDL开发精解与实例剖析》(VHDL development solution with fine examples of analysis)
- 2015-03-11 10:57:53下载
- 积分：1
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VHDL实现 8051 CPU核 Oregano Systems 8
VHDL实现 8051 CPU核 Oregano Systems 8-bit Microcontroller IP-Core-VHDL 8051 CPU nuclear Oregano Systems 8-bit Mic rocontroller IP-Core
- 2022-01-21 00:52:30下载
- 积分：1
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OQPSK_fading
OQPSK在AWGN和频率选择性衰落信道中的仿真(OQPSK the AWGN and frequency selective fading channel simulation)
- 2021-04-05 21:49:03下载
- 积分：1
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BLAST_QR1
MIMO系统采用QR检测算法的MATLAT仿真程序(mimo qr)
- 2009-07-15 08:09:01下载
- 积分：1
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NIOSII-Qsys_v1.3.1
黑金刚FPGA开发板使用说明文档，讲诉了NIOS和Qsys的详细开发步奏，值得学习。(KINGBOX FPGA development board documentation, recounts in detail the development of step-outs and Qsys NIOS, it is worth learning.)
- 2015-03-25 13:42:03下载
- 积分：1
