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FPGA秒表
基于 Xilinx Spartan 6 的、在七段译码管上显示、用按键控制计时开始、结束、逐秒累加功能的verilog代码，同时它是此开发板的一个demo工程，也是中山大学移动信息工程课程作业项目之一。希望对有需要参考的孩子有所帮助
- 2023-01-19 10:25:04下载
- 积分：1
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src
yuv444 与yuv422相互转换verilog语言(yuv444 to yuv422)
- 2021-01-20 14:38:41下载
- 积分：1
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ass1_3_safe
The objective of this project is to design and implement the controller for an electronic safe. You will interface a 16-button keypad to the NIOS boards. The combination code of the safe will be the last
- 2011-03-05 01:17:22下载
- 积分：1
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sinwave
使用verilog hdl语言编程正弦波信号，能仿真出结果(Can use verilog HDL language programming sine wave signal, the simulation results
)
- 2013-09-18 15:27:27下载
- 积分：1
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JJ213_program
卷积码（213）的编译码，VHDL语言编写的整个工程文件，带有仿真结果图。(Convolution code (213) codec, VHDL language of the whole project file with the simulation results shown in Fig.)
- 2020-12-27 19:29:02下载
- 积分：1
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error-detection-device
使用Verilog语言编程，在Quartus ii 上实现的误码检测装置，并通过单片机将误码结果显示在LCD上。本代码具有一定的工程实践价值。(Using the Verilog language programming, implemented on the Quartus ii error detection device, and the result of errors by the microcontroller on the LCD display. The code has some value engineering practice.)
- 2021-05-12 17:30:03下载
- 积分：1
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signal_capture
matlab 程序 伪随机码的捕获,我传的都是这方面的资料！(failed to translate)
- 2013-05-03 12:02:48下载
- 积分：1
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frequency divider
FPGA对系统50M时钟进行分频。FPGA最基本功能基础(FPGA Verilog program, key detection, program jitter elimination, jitter elimination, delay detection keys)
- 2019-04-27 23:35:12下载
- 积分：1
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szdyb
关于数字电压表的vhdl实现，有仿真程序，可以下载到板子中。(Vhdl digital voltage meter on the implementation of a simulation program can be downloaded to the board.)
- 2011-05-09 21:09:07下载
- 积分：1
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HDB3_encoder_QuartusPrj
说明： HDB3编码Quartus2 10.0的工程，modelsim仿真，有实物图、仿真图以及源程序，适合做通信原理课程设计的同学参考使用(HDB3 encoding Quartus2 10.0 project, modelsim simulation, there are physical map, simulation diagrams and source code, suitable for students of communication theory courses designed for reference use)
- 2011-03-25 08:35:32下载
- 积分：1
