登录
首页 » VHDL » 2位并行加法器初学者必看初步了解FPGA

2位并行加法器初学者必看初步了解FPGA

于 2023-07-28 发布 文件大小:130.45 kB
0 45
下载积分: 2 下载次数: 1

代码说明:

2位并行加法器初学者必看初步了解FPGA-two count

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • FPGA_实时时钟设计
    通过配置DS1302芯片来实现实时时钟的监测,我们通过通过控制2个按键来选择我们要在数码管上显示的时间,按下按键1我们来显示周几,按下按键2来显示年月日,不按显示时分秒,这样显示复合我们的数字表的显示(By configuring DS1302 chip to monitor the real-time clock, we select the time that we want to display on the digital tube by controlling 2 keys. Press key 1 to show the week, press the key 2 to show the year and month, not according to the display time, so that the display of the display of the display of our digital table.)
    2020-10-22 15:17:23下载
    积分:1
  • infrared_receive
    红外接收处理,根据外部波形记录波形的高低电平时间,从而得到波形数据。(Infrared receiver processing, according to the external waveform waveform record high and low times, resulting waveform data.)
    2013-09-27 11:09:02下载
    积分:1
  • 通信基带信号发生器的设计,采用单片机输入频率和波形,在FPGA中实现频率和波形生成...
    通信基带信号发生器的设计,采用单片机输入频率和波形,在FPGA中实现频率和波形生成-Communications base-band signal generator design, the use of single-chip input frequency and waveform, in the FPGA to achieve the frequency and waveform generation
    2022-03-14 12:44:53下载
    积分:1
  • ALU_74181_me
    学习ALU的设计方法。 2、用HDL语言采用行为描述的方法完成74181的逻辑设计 。(Learn the design method of ALU. 2, use HDL language to use behavioral description method to complete 74181 logical design.)
    2020-11-11 16:19:44下载
    积分:1
  • vlog_flash_20090712.tar
    说明:  NAND FLASH的多个仿真模型,可以用于接口设计的测试(NAND FLASH multiple simulation model that can be used for the test interface design)
    2009-08-05 21:14:07下载
    积分:1
  • 文章论述如何将向modelsim中添加仿真库,包括添加xilinx,altera,actel公司的仿真库的方法...
    文章论述如何将向modelsim中添加仿真库,包括添加xilinx,altera,actel公司的仿真库的方法-Article on how to add ModelSim simulation library, including the add xilinx, altera, actel the company
    2022-02-13 01:04:22下载
    积分:1
  • hdb3_v3
    Quartus环境下使用Verilog编写的HDB3编解码程序,RTL和时序仿真已过(Quartus under the environment of a HDB3 protocol procedures written in Verilog, RTL and timing simulation has be passed)
    2015-11-24 21:56:05下载
    积分:1
  • pipelined_fft_256
    verilog编写的并行256点fft代码(Verilog prepared parallel 256 points fft code)
    2017-06-28 21:56:53下载
    积分:1
  • 4-code
    设计一个十进制计数器,具有显示位置随计数时钟在八个数码管中左右滚动的功能。(Design of a decimal counter, a display position with the count clock in at around eight digital scrolling function.)
    2016-05-24 17:00:31下载
    积分:1
  • source
    FPGA与SDRAM 的 VHDL 接口设计(the interface of FPGA and SDRAM)
    2012-03-28 22:17:19下载
    积分:1
  • 696518资源总数
  • 104388会员总数
  • 18今日下载