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verilog编写的1024点的fft快速傅立叶变换代码
说明: FFT 1024 point, in 10 state
- 2020-12-18 20:29:11下载
- 积分:1
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verilog 写的 多功能数字钟
verilog 写的 多功能数字钟-verilog to write multi-functional digital clock
- 2023-03-18 14:30:04下载
- 积分:1
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apb_uart
基于APB总线的UART详细设计方案和实现(APB-based detailed design and implementation of UART)
- 2011-07-14 00:42:05下载
- 积分:1
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数字电路 贪食蛇游戏
VHDL 贪食蛇游戏用游戏把子上下左右控制蛇的方向,寻找吃的东西,每吃一口就能得到一定的积分,而且蛇的身子会越吃越长,身子越长玩的难度就越大,不能碰墙,不能咬到自己的身体,更不能咬自己的尾巴,等到了一定的分数,就能过关,然后继续玩下一关。
- 2022-03-17 03:15:55下载
- 积分:1
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cpsk_dpsk
数字通信系统相移键控CPSK信号和差分相移键控的调制与解调的VHDL代码(Phase shift keying digital communication system CPSK signals and differential phase-shift keying modulation and demodulation of the VHDL code for)
- 2009-11-06 16:11:03下载
- 积分:1
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USB_GPIF-II
fpga模拟两路视频,简单拼接后,经过GPIF II接口传出给cy2014,测试usb的吞吐量(fpga generate two lane video, and transmit them through GPIF II interface. test cy2014)
- 2017-06-02 18:50:04下载
- 积分:1
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这时manchesite编码,VERILOG语言,VHDL的找本站我发的帖子
这时manchesite编码,VERILOG语言,VHDL的找本站我发的帖子-manchesite time coding, VERILOG language, VHDL I find a site in a posting
- 2023-07-15 16:55:02下载
- 积分:1
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med_filter
基于图像处理的中值滤波VHDL源码,能够实现对图像的滤波(Based on the median filter VHDL source image processing, image filtering can be achieved)
- 2014-07-15 10:28:28下载
- 积分:1
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exercise3
用verilog实现dsp与Fpga接口的同步设计,其功能包括读写操作及四个功能模块,采用两个fifo实现不同时钟域的地址与数据的转换,在quartus ii11.0环境下运行,运行此程序之前需运行将调用fifo。(Dsp using verilog achieve synchronization with Fpga interface design, its features include read and write operations and four functional modules, using two different clock domains to achieve fifo address and data conversion in quartus ii11.0 environment to run, run this program required before running calls fifo.)
- 2013-08-30 11:12:09下载
- 积分:1
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频率计,VERILOG代码,含详细 中文注释.
频率计,VERILOG代码,含详细 中文注释.-Cymometer, VERILOG code, containing a detailed Chinese Notes.
- 2023-05-22 17:20:02下载
- 积分:1