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DDC
verilog语言实现的数字下变频设计。
在ALTERA的QUARTUS ii下实现。实用,好用。(Verilog language implementation of the digital down-conversion design. ALTERA at the implementation of QUARTUS ii. Practical, easy to use.)
- 2009-03-23 20:42:56下载
- 积分:1
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FCFS_PROJECT_A
FCFS (First Come First Served) with Database
- 2014-10-09 20:23:32下载
- 积分:1
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SV-Combinational-Logic
system Verilog combinational logic
- 2017-01-24 18:50:29下载
- 积分:1
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基于FPGA的lcd1202驱动
总4个模块。lcd_test顶层调用矩阵和lcd_1602,lcd_diver是写时序,lcd_ctrl是初始化及用户模式(即正常工作状态:发指令;数据和位置)。key_board矩阵驱动,已经过版级验证即按相应按键能在lcd上显示。
- 2022-09-13 18:30:04下载
- 积分:1
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HalfbandDec
基于FPGA开发的11阶半带升余弦FIR滤波器,用在阅读器基带滤波时的抽取滤波器使用,采用verilog语言实现。(Raised cosine FIR filter based FPGA development 11 order of half-band decimation filter used in reader baseband filtering, using verilog language implementation.)
- 2012-10-25 11:18:40下载
- 积分:1
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FPGA_Book_cd
《无线通信FPGA设计》包含的所有例子源码,包括matlab仿真和verilog源码,本书内容还是非常丰富的,涉及无线通信领域各个方面。不过对于一些比较新的技术,其FPGA实现部分过于简略,难以在工程中实用化。(" Wireless FPGA Design" contains all the examples source code, including the matlab simulation and verilog source code, the contents of this book is still very rich, involved in all aspects of the field of wireless communications. But for some relatively new technology, some of its FPGA implementation is too brief, it is difficult in practical engineering.)
- 2009-10-26 14:50:33下载
- 积分:1
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lanqiu24s8
篮球24s计时。计时器递减计数到零时,数码显示器显示‘0’并停止,同时发出报警信号(basketball 24 seconds)
- 2012-06-11 16:04:01下载
- 积分:1
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16ChannelDeserializer
说明: LVDS De-serialization
- 2019-06-20 14:53:25下载
- 积分:1
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基于AHB的SDRAM Verilog代码
该代码为基于AHB总线的SDRAM Verilog代码,对于进一步理解AHB协议有很大帮助,非常适合AMBA的初学者
- 2022-04-27 15:05:28下载
- 积分:1
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WCDMA_DPD
WCDMA数字直放站中数字预失真研究及其FPGA实现(WCDMA Digital Repeater digital pre-distortion and its FPGA implementation)
- 2011-10-16 19:24:50下载
- 积分:1