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跑马灯led_horse vhdl cpldfpga
跑马灯led_horse vhdl cpldfpga-led_horse vhdl cpldfpga
- 2022-12-03 00:40:03下载
- 积分：1
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mp3decoder
verilog实现mp3解码程序，包括testbench(mp3 decoder verilog implementation procedures, including the testbench)
- 2020-12-31 15:38:59下载
- 积分：1
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volt_mea_disp
本程序是用verilog 编写的模块，用来在lcd1602上显示用tlc549采样的电压值(This program is written in verilog module, used in lcd1602 display with tlc549 sampled voltage value)
- 2013-07-26 00:58:35下载
- 积分：1
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frame_decode_and_encode
一个用Verilog编写的编帧、解帧及码速匹配的程序，相当经典(Verilog prepared with a series of frames, frames and solutions yards speed matching procedures, rather classic!)
- 2006-07-12 15:10:07下载
- 积分：1
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VHDL 的想法
此代码包含非常有趣实现想法加密使用 vhdl 语言使用 Xilinx 的工具 ！希望你可以自定义和使用供您自己个人使用的这份工作 ！住宿已连接并且放松的感觉，要问的问题
- 2022-01-24 12:36:17下载
- 积分：1
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e1framerdeframer
E1成帧器和解帧器的FPGA实现源码，测试可用(E1 Framer deframer)
- 2012-12-07 12:10:06下载
- 积分：1
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Rotary Encoder
Reading the Rotary Encoder and indicating the selection through...
Rotary Encoder
Reading the Rotary Encoder and indicating the selection through a LED placed on the front panel.
Events counter for the Rotary Encoder and displaying the events on the front panel
Project: events counter for the rotary encoder and displaying the events on the SSD Pmod (Seven-Segments Display Programable module).
- 2022-05-24 04:15:56下载
- 积分：1
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verilog中调用门级电路的实验程序，实现了门级舰模
verilog中调用门级电路的实验程序，实现了门级舰模-call Verilog gate-level circuit of the experimental procedures, to achieve a gate-level ship-mode
- 2022-10-03 09:10:04下载
- 积分：1
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基于VHDL的UART控制器设计
UART模块的VHDL语言设计(Design of VHDL language based on UART module)
- 2017-11-13 23:56:26下载
- 积分：1
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RANGEN
2011年全国大学生电子设计竞赛E题“简易数字信号传输性能分析仪”fpga的控制代码，verilog编写；包括了M序列及同步时钟的提取等所有程序。(2011 National Undergraduate Electronic Design Contest E title "Simple digital signal transmission performance analyzer" fpga control code, verilog prepared including the M-sequence and synchronous clock extraction and all other programs.)
- 2020-10-27 17:09:59下载
- 积分：1
