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ADC0809 VHDL控制程序,基于VHDL语言,实现对ADC0809控制.
ADC0809 VHDL控制程序,基于VHDL语言,实现对ADC0809控制.-ADC0809 VHDL control procedures, based on the VHDL language, to achieve control of ADC0809.
- 2023-01-22 19:10:03下载
- 积分:1
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实现spi接口的传输,并多外接EEPROM读写数据
实现spi接口的传输,并多外接EEPROM读写数据-Spi interface to achieve the transfer, and multiple external EEPROM read and write data
- 2022-02-06 14:13:33下载
- 积分:1
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FPGA控制的SRAM接口不分的设计
FPGA控制的SRAM接口不分的设计-FPGA-controlled SRAM interface design, regardless of
- 2023-02-19 02:15:03下载
- 积分:1
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全部通过,是我的精心设计,完全满足初学者的要求。
全部通过,是我的精心设计,完全满足初学者的要求。-all passed, I was carefully designed, fully meet the requirements of beginners.
- 2022-02-20 15:52:11下载
- 积分:1
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Can be directly used for engineering applications of CRC checksum inside VHDL co...
可以直接用于工程应用的crc校验VHDL编码
里面有详细的规格书-Can be directly used for engineering applications of CRC checksum inside VHDL code has detailed specifications
- 2022-08-03 19:10:27下载
- 积分:1
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16QAM
基于FPGA 16QAM解调verilog代码,(16QAMdemoluator veriliog)
- 2021-02-23 23:49:39下载
- 积分:1
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usbd_ucos
说明: 基于ALINX AX7020硬件平台的USB-OTG通信程序。操作系统采用uCOS III v1.41,基本实现了双向USB2.0 块传输(Bulk Transfer)通信,zynq的PS端接收USB数据并回传至主机。经测试,主机端Window10系统采用libUSBK编程时,采用64字节的块时,传输速率可达210Mbps。zynq开发工具为Vivado2015.4,程序包中包含了全部的硬件和软件工程文档。(A USB-OTG communication project where an AX7020 platform is employed as USB device. The embeded operating system is uCOS III of version 1.41, and the FPGA toolchain is Vivado 2015.4. This project implements a full speed bidirectional USB2.0 bulk transfer. A test on Windows 10 host with libUSBK shows that the transfer speed is up to 201Mbps.)
- 2020-09-09 09:38:02下载
- 积分:1
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CU设计
计算机组成原理CU设计计算机组成原理CU设计计算机组成原理CU设计计算机组成原理CU设计计算机组成原理CU设计计算机组成原理CU设计计算机组成原理CU设计计算机组成原理CU设计计算机组成原理CU设计计算机组成原理CU设计计算机组成原理CU设计计算机组成原理CU设计
- 2023-06-25 08:00:03下载
- 积分:1
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SPI协议的VHDL/Verilog语言实现 SPI_Core
SPI协议的VHDL/Verilog语言实现。(SPI agreement VHDL/Verilog language.)
- 2020-06-27 10:00:02下载
- 积分:1
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Uses Verilog the HDL design, development board realizes in
Altera on the EP1S10S...
采用Verilog HDL设计,在Altera EP1S10S780C6开发板上实现
选取6MHz为基准频率,演奏的是梁祝乐曲
- Uses Verilog the HDL design, development board realizes in
Altera on the EP1S10S780C6 selects 6MHz is the datum frequency, the
performance is Liang wishes the music
- 2022-04-11 11:29:11下载
- 积分:1