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Hilbert
说明: 基于altera fpga的fir IP核实现希尔伯特变换,有matlab仿真(Based on Altera FPGA fir IP core to achieve Hilbert transform, matlab simulation)
- 2020-10-05 11:27:38下载
- 积分:1
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APB 总线
APB 总线。可以实现单个数据在总机与从机之间的读写功能(This can achieve the read and write functions of a single data between the master and the slave .)
- 2017-08-22 16:04:06下载
- 积分:1
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基于任意波形发生器的实现可编程逻辑器件…
基于可编程逻辑器件实现任意波形发生器VHDL源代码-Programmable logic device based on the arbitrary waveform generator implementation VHDL source code
- 2023-05-09 22:45:03下载
- 积分:1
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train_controler
train controler by verilog
- 2012-09-03 16:16:23下载
- 积分:1
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SV-Combinational-Logic
system Verilog combinational logic
- 2017-01-24 18:50:29下载
- 积分:1
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Verilog_SimpleCalculator-master
这是一个计算器的Verilog代码,可实现加减乘除等基础功能(calcultor for you to do some reserches.)
- 2017-12-24 10:24:59下载
- 积分:1
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m68000
VHDL code for MC68000
- 2011-06-21 17:17:00下载
- 积分:1
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层合板刚度
层合板的刚度的计算和验算,包括拉伸刚度A、弯曲刚度D以及耦合刚度B。
首先要给定层合板的各个参数,具体有:层合板的层数N;各单层的弹性常数E1、E2、 、G12;各单层对应的厚度;各单层对应的主方向夹角 。(The stiffness of laminated plates is calculated and checked, including tensile stiffness, A, flexural stiffness, D and coupling stiffness B. First of all, it is necessary to give the parameters of laminated plates, such as the number of plies N, the elastic constants of each layer, E1, E2, and G12, the thickness of each monolayer, and the angle of the main direction corresponding to each single layer.)
- 2021-01-18 09:28:43下载
- 积分:1
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Detailed description of the FPGA design flow of the entire FPGA design flow full...
详细的说明了FPGA设计的整个流程
FPGA设计全流程Modelsim>>Synplify.Pro>>ISE-Detailed description of the FPGA design flow of the entire FPGA design flow full Modelsim> > Synplify.Pro> > ISE
- 2022-11-01 22:10:02下载
- 积分:1
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适用于FPGA的SOPC方面的元器件添加,如COMPNENT
适用于FPGA的SOPC方面的元器件添加,如COMPNENT-Applicable to FPGA-SOPC area to add components, such as COMPNENT
- 2022-09-20 17:30:03下载
- 积分:1