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JTAG
边界扫描技术相关资料，含各个模块的介绍。很有参考价值。(JTAG TAG CONTROLLER)
- 2016-02-24 19:10:03下载
- 积分：1
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interpolation_shaping_filter
内插成型滤波器的FPGA实现，可根据需要配置不同的内插倍数，Quarter II环境编译，可直接使用(Interpolation shaping filter FPGA, can be equipped with different interpolation factor, Quarter II compiler environment, can be used directly)
- 2013-11-12 21:13:46下载
- 积分：1
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i2c ADT75温度传感器
I2C温度传感器ADT75的控制源码 使用verilog 状态机实现 易入门-I2C for ADT75 temperature sensor
- 2022-02-14 14:53:33下载
- 积分：1
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SASX
说明： Use of Kalman and EKF on two-phase permanent magnet synchronous motor of the state estimate CDCDCDCDCCC
- 2020-06-24 11:40:02下载
- 积分：1
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Divider-vhdl
This is a divider, which is depicted as well.
It is a programming language Vhdl.
- 2013-09-29 18:28:11下载
- 积分：1
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SRAM6bit
sram 6bit仿真模型，verilog编写(sram 6bit simulation model, verilog prepared)
- 2021-03-16 13:59:22下载
- 积分：1
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由avalen总线转接i2c总线的vhdl程序 可应用于nios嵌入式系统
由avalen总线转接i2c总线的vhdl程序 可应用于nios嵌入式系统-By avalen bus adapter i2c bus VHDL program can be applied to Nios Embedded Systems
- 2022-02-28 11:19:17下载
- 积分：1
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write VHDL 8051 kernel, available, convenient, can be downloaded interested in t...
VHDL写的8051内核,可用的,好用,有兴趣可下载,在外国网站下载的-write VHDL 8051 kernel, available, convenient, can be downloaded interested in the foreign website
- 2022-01-25 17:39:39下载
- 积分：1
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FFT_top_5
方案组成模块及系统框图
本方案设计主要由以下模块组成
1：顶层模块
2：数据输入排序模块
3：系统控制模块
4：RAM控制器模块
5：ROM控制器模块
6：蝶型单元模块(Program composition module and system diagram
The design of this scheme is mainly composed of the following modules
1: top module
2: data input sorting module
3: system control module
4:RAM controller module
5:ROM controller module
6: butterfly type unit module)
- 2017-08-23 16:23:54下载
- 积分：1
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MCU_V_PWM_16bit
单片机通过总线，将占空比和频率送到CPLD/FPGA中，并控制PWM输出.采用Verilog HDL语言编写。(Microcontroller by bus, the duty cycle and frequency sent to the CPLD/FPGA in, and control the PWM output. Using Verilog HDL language.)
- 2020-10-29 09:19:57下载
- 积分：1
