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RS(204-188)decoder_verilog
采用verilog实现的有限域GF(28)弱对偶基乘法器，本原多项式: p(x) = x^8 + x^4 + x^3 + x^2 + 1 ，多项式基: {1, a^1, a^2, a^3, a^4, a^5, a^6, a^7}，弱对偶基: {1+a^2, a^1, 1, a^7, a^6, a^5, a^4, a^3+a^7}(Verilog achieved using the finite field GF (28) weak dual basis multiplier)
- 2016-06-12 16:31:51下载
- 积分：1
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uart
uart发射机Verilog HDL代码(Verilog HDL code uart transmitter)
- 2011-05-21 21:37:01下载
- 积分：1
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8.8-URAT-VHDL
URAT VHDL程序与仿真 URAT the VHDL program and Simulation
(URAT the VHDL program and Simulation
)
- 2012-04-09 20:53:45下载
- 积分：1
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24小时计时时钟
说明： 实现24小时计时，因为位数不够，这里是12进位，可自行调整进位数(Realize 24-hour timing, because the number of digits is not enough, here is 12 carry, you can adjust the carry number by yourself.)
- 2020-06-23 19:40:01下载
- 积分：1
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add
流水线乘法器与加法器
开发环境：Modelsim（verilog hdl）(Multiplier and adder pipeline development environment: Modelsim (verilog hdl))
- 2009-05-18 12:19:24下载
- 积分：1
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AD
说明： FPGA实现的AD采样控制程序的源码，欢迎大家下载(FPGA implementation of the AD sampling control)
- 2021-04-14 21:18:55下载
- 积分：1
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DDS-Waveform-generator
采用FPGA实现的DDS波形发生器源码，可以实现频率幅值变换、正弦波、方波、三角波输出，输出频率可达1MHz(FPGA implementation of the DDS waveform generator source frequency amplitude transform, sine wave, square wave, triangle wave output, the output frequency up to 1MHz)
- 2012-06-29 23:20:58下载
- 积分：1
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phone
用DE0开发板实现电话计费器，基本功能：可设置通话模式，能初始化话费余额，拨动开关可进入通话模式，并根据通话时间和相应通话模式扣除相应的费用。通话过程中能够通过开关切换显示通话时间和话费余额，并可暂停通话。压缩包里有详细的WORD文档的说明，包括波形仿真和DE0的引脚功能介绍。(Implemented by DE0 board telephone billing, basic function: to set the call mode, you can initiate credit balance, toggle switch into the talk mode, and deduct the cost of a call based on call time and the corresponding mode. Call talk time and can be displayed by switching credit balance, and mute. Compression bag has a detailed description of WORD documents, including the waveform simulation and DE0 pin function description.)
- 2020-11-06 13:19:49下载
- 积分：1
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AD7980
AD9850 VERILOG代码 硬件验证过，可以使用。
- 2021-05-07 15:37:36下载
- 积分：1
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dw_ahb_dmac_db
It is Synopsys dmac controller databook
- 2020-10-10 10:27:34下载
- 积分：1
