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vga_interface_requiring_core_regeneration
vga interface with text rom. font size 80x40. core need core regeneration.
- 2013-05-19 02:09:10下载
- 积分：1
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Simulate
FPGA控制AD逐点采集信号，并将AD转换后的数据串行发送出去。(FPGA to control the signal sampling point by point AD, AD conversion and serial data sent.)
- 2021-04-14 21:08:55下载
- 积分：1
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key_xiaodou
说明： 该资料是用vhdl编写的按键消抖程序，按键消抖在使用按键的数字电路中非常重要，如果不对按键信号进行处理，有可能会出现大量错误的按键信号。文件key_xd.vhd是按键消抖程序，文件key_xd.vwf是仿真波形文件。该程序已经通过仿真测试，并且在电路板上调试通过，效果理想。(The information is written in the key consumer vhdl shaking procedures, key consumer shaking in digital circuits using the buttons is very important, if not key signal processing, there may be a lot of the wrong button signal. File key_xd.vhd is key consumer shake procedure is the simulation waveform file key_xd.vwf file. The program has been tested by simulation and debugging in circuit board by, the results are satisfactory.)
- 2010-04-26 16:13:57下载
- 积分：1
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QAM
OFDM中的16QAM星座映射的实现实现详细代码(In OFDM 16QAM constellation mapping to achieve the realization detailed code)
- 2021-03-11 17:59:25下载
- 积分：1
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verilog HDL
说明： DS18B20温度模块，LCD1602显示(DS18B20 Temperature Module, LCD1602 Display)
- 2020-09-04 15:08:06下载
- 积分：1
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jitter_eliminate
verilog描述的实用消抖电路，采用三个D触发器和一个JK触发器。使用emacs编写源文件，iverilog仿真通过，内有png仿真图像截屏(verilog description of the practical elimination shake circuit, using three D flip-flop and a JK flip-flop. Prepared source files using the emacs , iverilog simulation adopted, within the simulation images png screenshots)
- 2009-11-24 15:51:44下载
- 积分：1
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24小时计时时钟
实现24小时计时，因为位数不够，这里是12进位，可自行调整进位数(Realize 24-hour timing, because the number of digits is not enough, here is 12 carry, you can adjust the carry number by yourself.)
- 2020-06-23 19:40:01下载
- 积分：1
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C-V2X-master
说明： LTE is an abbreviation for Long Term Evolution.
- 2019-06-29 01:08:09下载
- 积分：1
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hidejj
实现线性反馈移位寄存器的verilog实现(lfsr use verilog for the zip)
- 2017-08-02 14:23:12下载
- 积分：1
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PLL
FPGA板上的锁存器PLL控制代码（verilog代码）(FPGA board latch the PLL control code (Verilog code))
- 2021-03-19 17:29:19下载
- 积分：1
