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alter FPGA,包含sdram的nios系统开发实验完整工程文件
alter FPGA,包含sdram的nios系统开发实验完整工程文件-nios develop based nios IDE6.0,system involved an sdram
- 2022-02-13 18:25:41下载
- 积分:1
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seven_persons
自己写的7人表决器的verilog程序,实现4人以上通过则通过的功能。(Seven people to write their own voting machine verilog program to achieve four or more people pass through function.)
- 2013-08-10 07:15:06下载
- 积分:1
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帧同步信号FPGA实现代码(可正常运行)
通信系统帧同步信号的设计与实现,巴克码识别器系统完整VHDL程序,本人课程设计,完全能正常运行,程序运行环境为Quartus II 7.2 (32-Bit),win7系统。编译码模块、分频模块、门限设置模块、仿真电路和程序都有。相互交流,共同学习!!
- 2022-03-24 07:45:00下载
- 积分:1
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oc_i2c_master_top_v92
I2C IP for Quartus V9.0 sp2, can used in SOPC builder.
- 2009-10-10 10:43:18下载
- 积分:1
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air
空调温控电路有限状态自动机,
有TEMP_HIGH和TEMP_LOW
分别与传感器相连用语检测室内温度.-air-conditioning temperature control circuit finite state automaton, and TEMP_LOW TEMP_HIGH with sensors connected to the indoor temperature detection terminology.
- 2022-04-25 13:00:13下载
- 积分:1
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A Dec example written in VHDL.
A Dec example written in VHDL.
- 2022-03-14 22:18:50下载
- 积分:1
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AD7938controllor-VHDL
说明: VHDL语言的有限状态机法控制8位/12位自动转换通道模数转换器AD7938(VHDL, FSM method to control 8-bit/12-bit ADC AD7938 auto-conversion channel)
- 2011-04-12 11:21:55下载
- 积分:1
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本文是自已写的电子密码锁的详细开发过程,用的是Modelsim进行仿真实现,打开文档lzp...
本文是自已写的电子密码锁的详细开发过程,用的是Modelsim进行仿真实现,打开文档lzp-This article is written in their own electronic locks detailed development process, using a ModelSim simulation achieved, open the document lzp
- 2022-01-25 15:10:58下载
- 积分:1
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fifo
异步FIFO
输入: 16bit
输出:16bit
深度:256(Asynchronous FIFO
Input: 16bit
Output: 16bit
Depth: 256)
- 2017-07-10 14:02:36下载
- 积分:1
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跑马灯led_horse vhdl cpldfpga
跑马灯led_horse vhdl cpldfpga-led_horse vhdl cpldfpga
- 2022-12-03 00:40:03下载
- 积分:1