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dp_xiliux the CPLD Verilog design experiments, serial presentation. code test.
dp_xiliux 的 CPLD Verilog设计实验,串口演示.代码测试通过. -dp_xiliux the CPLD Verilog design experiments, serial presentation. code test.
- 2022-11-12 18:25:03下载
- 积分:1
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在SOPC下制作自定义部件(PWM发生器)的源程序,包括硬件描述HDL文件和驱动程序文件...
在SOPC下制作自定义部件(PWM发生器)的源程序,包括硬件描述HDL文件和驱动程序文件-Produced in the SOPC custom component (PWM generator) of the source, including hardware description HDL files and driver files
- 2022-03-19 04:54:11下载
- 积分:1
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dianzhen
如果需要用verilog设计一项比较简单的功能,那么这个浅显易懂的程序能让你很快明白点阵的设计方法,尤其是对那些初学者(If you need to use a relatively simple verilog design features, then this easy to understand design of the program allows you to quickly understand the lattice method, especially for those who are beginners)
- 2014-01-16 16:13:53下载
- 积分:1
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利用FPGA实现的脉宽测试技术,基于VHDL,测试误差为时钟周期
利用FPGA实现的脉宽测试技术,基于VHDL,测试误差为时钟周期-Use of FPGA technology to achieve the pulse-width test, based on VHDL, test error of clock cycles
- 2022-06-26 11:28:29下载
- 积分:1
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基于CPLD的交通信号灯的实现
基于CPLD的交通信号灯的实现,使用VHDL语言,使用不同颜色的二极管分别代表红黄绿三种信号灯。在数码管上可以分别显示倒计时。
- 2022-03-12 13:41:19下载
- 积分:1
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StepMotor_CurrentLoop
说明: 实现二项混合式步进电机的驱动,和步进电机的细分程序。(The driving of binomial hybrid stepper motor and the subdivision program of stepper motor are realized.)
- 2020-06-21 02:20:01下载
- 积分:1
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sobel
基于FPGA的Spartan-6系列的SOBEL算法实现(Implementation of SOBEL Algorithm Based on FPGA)
- 2018-05-09 15:25:33下载
- 积分:1
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123.rar
請設計一個8位元移位暫存器,規格如下:
當控制線S1,S2輸入為00時,平行載入;
當控制線S1,S2輸入為01時,在一時脈內向右shift 1位元;
當控制線S1,S2輸入為10時,在一時脈內向右shift 2位元;
當控制線S1,S2輸入為11時,在一時脈內向右shift 3位元
(Serial Adder)
- 2009-12-08 00:02:56下载
- 积分:1
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一个同步有限状态机(FSM)的设计是一个数字的共同任务…
Designing a synchronous finite state machine (FSM) is a common task for a digital
logic engineer. This paper discusses a variety of issues regarding FSM design using
Synopsys Design Compiler. Verilog and VHDL coding styles are presented, and
different methodologies are compared using real-world examples.
- 2022-01-26 02:12:10下载
- 积分:1
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verilog hdl coding DDR sdram control for fpga
verilog hdl coding DDR sdram control for fpga -verilog hdl coding DDR sdram control for fpga
- 2022-03-23 21:20:26下载
- 积分:1