-
VMD642_CPLD
本例程位于 VMD642_CPLD目录中。
使用 CPLD 实现辅助译码、LED 指示灯控制、看门狗等各种逻辑控制电路。源程序使
用 Verilog HDL书写,编译开发系统使用 Cypress公司的 Warp 6.3。(This routine is located VMD642_CPLD directory. Using CPLD implementation auxiliary decoding, LED indicator control, watchdog, and other logic control circuitry. Written using Verilog HDL source code, the compiler development system using Cypress' s Warp 6.3.)
- 2013-09-13 13:59:52下载
- 积分:1
-
VHDL source VHDL source VHDL source
VHDL源码 VHDL源码 -VHDL source VHDL source VHDL source
- 2022-01-26 18:08:58下载
- 积分:1
-
Written in the quaters of the size of the comparator output, verilog language wr...
在quaters下写的比较数的大小输出,verilog语言写的,具有状态机和存储器-Written in the quaters of the size of the comparator output, verilog language written with the state machine and memory
- 2022-02-26 07:00:13下载
- 积分:1
-
wp_max_flash
FPGA中FLASH配置控制源码,VHDL和Verilog(FPGA source code in the FLASH configuration control, VHDL and Verilog)
- 2007-12-11 15:57:15下载
- 积分:1
-
关于寄存器重命名register reallocation,VHDL
关于寄存器重命名register reallocation,VHDL-Register on rename register reallocation, VHDL
- 2022-02-09 20:31:31下载
- 积分:1
-
代码基于VHDL语言的个文化代码有用的但是可能有错误下在是倾销心...
代码基于VHDL语言的个文化代码有用的但是可能有错误下在是倾销心-VHDL code based on the cultural code useful but may be under the wrong heart is dumping
- 2022-04-13 03:11:13下载
- 积分:1
-
tb_axi4
介绍如何使用vivado来调用和封装IP核,测试AXI4总线的三种功能协议。(It describes how to use vivado to call and package IP core test three functions AXI4 bus protocol.)
- 2020-07-03 08:40:01下载
- 积分:1
-
dma_hussam
verilog code for dma
- 2021-04-24 19:09:04下载
- 积分:1
-
UART
基于FPGA设计的串口发送及接收程序,波特率可调(FPGA - based serial port sending and receiving)
- 2020-06-18 23:20:01下载
- 积分:1
-
明白4
实现了一个四层单电梯控制系统。门可以自动开关,也可以手动开关。代码可以集成,不超过驱动的现象。
- 2022-04-10 00:20:47下载
- 积分:1