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verilog HDL语言编写的键盘扫描程序，考虑以确定关键的博…
Verilog HDL编写的键盘扫描程序，考虑了判断按键弹起的问题。程序按一定的频率用低电平循环扫描行线，同时检测列线的状态，一旦判断有一列为低则表示有键被按下，停止扫描并保持当前行线的状态，再读取列线的状态从而得到当前按键的键码；等待按键弹起：检测到各列线都变成高点平后，重新开始扫描过程，等待下一次按键。-Written in Verilog HDL keyboard scanner, taking into account to determine key bounce problem. Program according to a certain frequency of scan lines with low-level circulation lines, while testing out the state line, once the judge has said there is a classified as low-key is pressed, stop the scan and to maintain the current line-line state, and then read out line state to get the current keys key codes to wait for key pop-up: To detect the lines at all out into a high level after the re-start the scanning process, waiting for the next key.
- 2022-05-07 15:33:47下载
- 积分：1
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CLZ32
针对32位MIPS微处理器中CLZ指令（对单个字高位连零进行计数）的实现电路，使用了类似于超前进位的逻辑结构。包含测试文档，以及Design
Compile所用的环境和脚本。(The CLZ instruction counts the number of leading zeros in a word. The 32-bit word in the GPR rs is scanned from most-significant to least-significant bit.The number of leading zeros is counted and the result is written to the GPR rd. If
all 32 bits are cleared in the GPR rs, the result written to the GPR rd is 32. )
- 2021-03-31 19:39:08下载
- 积分：1
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PWM for control of motors
PWM for control of motors
- 2022-07-25 05:36:51下载
- 积分：1
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sample_tcam.tar
verilog RTL code for simple TCAM
- 2014-06-25 15:50:08下载
- 积分：1
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基于fpga的液晶驱动开发过程相关资料，用于借鉴和学习
基于fpga的液晶驱动开发过程相关资料，用于借鉴和学习-Fpga-based LCD driver development process relevant information, for reference and learning
- 2023-02-14 14:50:04下载
- 积分：1
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airthmatic & logic unit
airthmatic & logic unit
- 2023-02-23 08:10:03下载
- 积分：1
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dpll
用verilog编写的全数字锁相环，包括鉴相器，模K计数器，加减脉冲模块和分频模块，都经过验证(verilog based digital phase lock loop design, including phase detector,mode K counter, increment/decrement counter and frequency divider )
- 2014-04-22 08:36:53下载
- 积分：1
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基于VHDL数字频率计
基于vhdl可用的数字频率计，误差较小，精准度较高。文件中还包含了与arm的通信模块、
- 2022-03-05 17:19:11下载
- 积分：1
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FSK_FPGA
FSK模拟信号源，利用ISE7.1或以上环境打开。(FSK signal simulator.The project can be open in ISE7.1 or upgrade version.)
- 2009-07-16 17:09:07下载
- 积分：1
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QC_LDPC译码器的FPGA设计
说明： LDPC码的FPGA实现，用verilog语言编写(FPGA implementation of LDPC code, written in Verilog language)
- 2019-11-15 06:04:33下载
- 积分：1
