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cic_compiler_ds613
说明： 国外的CIC补偿滤波器设计文件，非常有用(Abroad, CIC compensation filter design files, very useful)
- 2010-03-21 13:56:49下载
- 积分：1
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This code implements the shift register functions, beginners can learn to learn
本代码实现了移位寄存器功能，初学者可借鉴学习-This code implements the shift register functions, beginners can learn to learn
- 2023-01-14 23:45:03下载
- 积分：1
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开发系统上采用的时钟信号的频率是20MHz，可分别设计计数器对其计数，包括计秒、分、小时、日、周、月以及年等。在每一级上显示输出，这样就构成了一个电子日历和时钟...
开发系统上采用的时钟信号的频率是20MHz，可分别设计计数器对其计数，包括计秒、分、小时、日、周、月以及年等。在每一级上显示输出，这样就构成了一个电子日历和时钟的模型。为了可以随意调整计数值，还应包含设定计数初值的电路-Development system using the clock signal frequency is 20MHz, the design can be counter to its count, including seconds, minutes, hours, days, weeks, months and years. At every level to show the output, thus constitutes an electronic calendar and clock models. Can also adjust the order value, should also be included in setting the initial count circuit
- 2022-08-07 06:47:58下载
- 积分：1
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UG586-7SeriesDMIUserGuide
UG586 - Zynq-7000 All Programmable SoC and 7 Series Devices Memory Interface Solutions v2.3 User Guide ( ver2.3, 18511 KB )(UG586- Zynq-7000 All Programmable SoC and 7 Series Devices Memory Interface Solutions v2.3 User Guide ( ver2.3, 18511 KB ))
- 2015-02-05 20:02:21下载
- 积分：1
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verilog-code-style-specification
企业用verilog代码风格规范 本规范规定了IC设计项目开发过程中VerilogHDL源代码的编写总则、要求及模板文件。(Enterprises with verilog code style guide for the preparation of this specification General IC design project development process VerilogHDL source code, requirements and template files.)
- 2015-05-31 16:06:37下载
- 积分：1
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pipeline_FPGA
FPGA流水线设计的资料，可以作为学习FPGA开发并行操作的一个经典教材，具有很好的指导作用。(FPGA pipeline design information can be developed as a learning FPGA parallel operation of a classic textbook, has a good guide.)
- 2011-07-02 12:00:57下载
- 积分：1
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QAM
OFDM中的16QAM星座映射的实现实现详细代码(In OFDM 16QAM constellation mapping to achieve the realization detailed code)
- 2021-03-11 17:59:25下载
- 积分：1
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rtl
基于脉动结构的有限域乘法器，verilog代码(Based on the pulse of the structure of finite field multipliers, verilog code)
- 2010-01-04 11:48:50下载
- 积分：1
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a lot of examples and test code, useful for beginners, it is easy to get started
有很多例子及测试代码，对初学者很有帮助，很容易上手-a lot of examples and test code, useful for beginners, it is easy to get started
- 2022-02-02 14:25:45下载
- 积分：1
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my
说明： 64位数据的CRC-32校验的，Verilog实现，算法并行优化(64-bit data CRC-32 checksum, Verilog implementation of a parallel optimization algorithm)
- 2011-09-17 19:36:16下载
- 积分：1
