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vhdl实现vga接口设计，非常实用的一段代码，学习用
vhdl实现vga接口设计，非常实用的一段代码，学习用-vhdl achieve vga interface design
- 2023-05-25 04:40:03下载
- 积分：1
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FPGA控制AG9226代码
FPGA控制AG9226进行采样的代码,并用signaltap测试了一下其正确性
- 2022-07-21 15:41:56下载
- 积分：1
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rs-codec-8-16
RS[255,223]纠错码verilog源码，包含编码和解码模块，以及testbench等。(Verilog source code for RS[255,223] encoder and decoder, with testbench included.)
- 2021-04-28 15:58:44下载
- 积分：1
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电梯控制器程序设计与仿真的vhdl源代码
电梯控制器程序设计与仿真的vhdl源代码-Elevator controller design and simulation of vhdl source code
- 2022-04-08 14:05:19下载
- 积分：1
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用于FPGA的huffman算法的HDL编码，包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。...
用于FPGA的huffman算法的HDL编码，包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。-The huffman algorithm for FPGA HDL coding, including VHDL and Verilog code. Can be used in JPEG and MPEG compression algorithms.
- 2022-03-05 20:13:50下载
- 积分：1
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read-string-from-FLASH
read data of type character from flash memory
- 2013-09-08 03:49:15下载
- 积分：1
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Design-of-taxi-meter-Based-on-FPGA
本文分析了当前国内外出租车计费系统的基本组成和工作原理及主要的两种设计方式:基于单片机的设计方式和基于FPGA的设计方式；并对这两种实现方式的优点和缺点进行分析，比较后确定本系统的方案：基于FPGA的出租车计费系统的设计。(This paper analyzes the current taxi charging system at home and abroad, working principle and basic components of two major design approach: the design methods based on single chip FPGA-based design approach and the two implementations to analyze the strengths and weaknesses, After comparing the program to determine the system: FPGA-based taxi billing system.)
- 2011-05-11 15:38:37下载
- 积分：1
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Verilog module containing a synthesizable CRC function
//* polynomial: (0 1 8)...
Verilog module containing a synthesizable CRC function
// * polynomial: (0 1 8)
// * data width: 8-Verilog module containing a synthesizable CRC function
//* polynomial: (0 1 8)
//* data width: 8
- 2022-08-18 21:19:43下载
- 积分：1
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FPGA_5
无SDRAM的PCI采集,给出PCI采集的FPGA程序，桥芯片也为PLX9054，已验证通过(No SDRAM, PCI capture, given FPGA PCI acquisition program, bridge chips for PLX9054, has been verified by)
- 2015-01-07 22:57:46下载
- 积分：1
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MCU_V_PWM_16bit
单片机通过总线，将占空比和频率送到CPLD/FPGA中，并控制PWM输出.采用Verilog HDL语言编写。(Microcontroller by bus, the duty cycle and frequency sent to the CPLD/FPGA in, and control the PWM output. Using Verilog HDL language.)
- 2020-10-29 09:19:57下载
- 积分：1
