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wom_kg
ϵͳʱ
- 2006-03-13 15:09:50下载
- 积分：1
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test_uart
基于fpga的uart串口通信协议，64位数据(Uart communication protocol based on fpga, 64-bit data)
- 2017-08-09 17:35:47下载
- 积分：1
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脉动进位加法器
设计的结构是纹波进位加法器，但执行的操作是加法和减法，两种操作都是32位的，具体取决于控制信号。如果控制信号为“1”，则选择减法，然后选择“0”，然后选择加法
- 2022-02-02 17:58:16下载
- 积分：1
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Version1
小波包分解，重构轴承振动信号，Hilbert包络，FFT进行频谱分析，以获得轴承故障频率。(Wavelet packet decomposition, reconstruction of bearing vibration signal, Hilbert envelope, FFT spectrum analysis to obtain the bearing fault frequencies.)
- 2013-07-17 11:37:05下载
- 积分：1
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FPGA实现12路pwm
采用vhdl语言实现12路的pwm波控制。-Language implementation using vhdl wave pwm control of the road 12.
- 2022-04-28 14:34:54下载
- 积分：1
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2018全国大学生FPGA大赛封闭测试上机题
说明： 2018全国大学生FPGA创新设计大赛南京总决赛封闭测试题目，以及自己编写的verilog和testbench，欢迎学习借鉴(The closed test topic of the 2018 National Undergraduate FPGA innovation design competition Nanjing finals, as well as Verilog and testbench compiled by ourselves, are welcome to learn)
- 2020-11-23 22:39:33下载
- 积分：1
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1024-point-FFT-in-verilog.pdf
1024 点得快速傅里叶变换算法 FPGA in verilog(1024 point FFT on a FPGA written in verilog)
- 2014-03-26 22:56:23下载
- 积分：1
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Риторика_Зачетная работа
说明： access must be conf urr arr
- 2019-05-29 20:23:53下载
- 积分：1
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VHDL实现SPI功能源代码
VHDL实现SPI功能源代码
-- The SPI bus is a 3 wire bus that in effect links a serial shift
-- register between the "master" and the "slave". Typically both the
-- master and slave have an 8 bit shift register so the combined
-- register is 16 bits. When an SPI transfer takes place, the master and
-- slave shift their shift registers 8 bits and thus exchange their 8
-- bit register values.-SPI realize the functional VHDL source code The SPI bus is a 3 wire bus that in effect links a serial shift register between the
- 2022-01-26 00:50:40下载
- 积分：1
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在quartus中使用IP核的实际例子与流程
在quartus中使用IP核的实际例子与流程-The use of IP in the Quartus practical examples and nuclear flow
- 2022-08-07 01:33:34下载
- 积分：1
