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ConvolutionWithViterbiDecoding
QPSK调制下的（5,7）卷积码的编码和维特比译码与BPSK调制下（5,7）卷积码的编码和维特比译码的BER特性(QPSK modulation under (5,7) convolutional code encoding and Viterbi decoding and BPSK modulation (5,7) convolutional code encoding and Viterbi BER characteristic)
- 2020-12-12 20:09:15下载
- 积分：1
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同步串行数据发送电路SSDT的基本功能是将并行数据转换成串行数据并进行同步发送。系统写入和读出时序完全兼容Intel8086时序。
系统以同步信号开始连续发...
同步串行数据发送电路SSDT的基本功能是将并行数据转换成串行数据并进行同步发送。系统写入和读出时序完全兼容Intel8086时序。
系统以同步信号开始连续发送四个字节，在发送中出现5个1时插入一个0，在四个数据发送结束而下一次同步没有开始之前，发送7FH，这时中间不需要插入零
-synchronous serial data transmission circuit SSDT the basic function is to convert parallel data into serial and the same this step. System write and read sequential fully compatible Intel8086 timing. Synchronized signal system to start sending four consecutive bytes, in this emerging 5 1:00 insert a 0, at the end of four data sent and the next synchronization not started before, sending seven FH, then the middle is not inserted
- 2023-05-29 03:45:03下载
- 积分：1
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计数器的VHDL语言程序实现1
VHDL语言编写的计数器程序，实现1到9999计数，并动态扫描显示，带清零和暂停功能，课上作业自编程序-VHDL language of the counter program to achieve 1-9999 counts, and the dynamic scan showed, with Clear and suspension of functions, classes, on a self-compiled programs
- 2022-01-21 03:16:50下载
- 积分：1
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VGA
verilog vga 图像处理(verilog vga)
- 2013-10-15 19:00:16下载
- 积分：1
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stepper_motor
control stepper motor by fpga card with vhdl program
- 2012-01-08 02:34:17下载
- 积分：1
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我用VHDL写的正弦，用FPGA内部ROM，有仿真testbench,在quartus里可以运行。在板子里已经验证...
我用VHDL写的正弦，用FPGA内部ROM，有仿真testbench,在quartus里可以运行。在板子里已经验证-I used to write VHDL sinusoidal, using FPGA internal ROM, has simulation testbench, you can run in Quartus. Yard has already been verified in the plates
- 2022-07-25 14:12:00下载
- 积分：1
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JOP of RAM VHDL source code, classic classics, difficult to find a good price.
JOP的RAM VHDL源码，经典的经典，不易找到的好东东，-JOP of RAM VHDL source code, classic classics, difficult to find a good price.
- 2022-10-01 16:00:03下载
- 积分：1
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对于多个子分频的Verilog代码
verilog分频器代码
分为偶数倍分频和奇数倍分频两个verilog源文件 附带一个说明文档-divider verilog code for multiple sub-divided into even and odd frequency divider several times with a two verilog source files documentation
- 2022-10-15 03:40:06下载
- 积分：1
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I2C控制器源代码，Verilog HDL语言，可以直接调用
I2C控制器的源代码，Verilog HDL语言编写，可以直接调用-I2C controller source code, Verilog HDL language, you can directly call
- 2023-04-28 04:45:03下载
- 积分：1
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tlm
tlm基本框架，生产消费模型例子
tlm基本框架，生产消费模型例子
tlm基本框架，生产消费模型例子(tlm basic framework, examples of production and consumption model)
- 2010-01-27 17:31:47下载
- 积分：1
