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dingshi
定时器加数码管显示源码，以及test bench测试模块源码，经modelsim仿真结果正确(Timer plus digital display source code, and test bench test module source code, by modelsim simulation results are correct)
- 2013-07-27 10:34:41下载
- 积分：1
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spwm
关于SPWM调制设计VHDL代码
关于SPWM调制设计VHDL代码(SPWM modulation on the design of VHDL code design on the VHDL code modulation SPWM)
- 2021-03-16 09:19:22下载
- 积分：1
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zidong-shouhuoji
用VERILOG实现自动售货机功能，运行正确，希望有帮助(Use VERILOG implementation vending machine function, correct operation, hope to have help)
- 2014-01-05 20:42:49下载
- 积分：1
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一个同步有限状态机（FSM）的设计是一个数字的共同任务…
Designing a synchronous finite state machine (FSM) is a common task for a digital
logic engineer. This paper discusses a variety of issues regarding FSM design using
Synopsys Design Compiler. Verilog and VHDL coding styles are presented, and
different methodologies are compared using real-world examples.
- 2022-01-26 02:12:10下载
- 积分：1
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其基于FIFO的设计
its a Fifo BASED design
i also Interface DAC2904
- 2023-02-01 15:35:04下载
- 积分：1
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VHDL语言100例详解，北京理工大学ASIC研究生出版，这里是1
VHDL语言100例详解，北京理工大学ASIC研究生出版，这里是1-20个examples-VHDL language of 100 cases explain, Beijing Institute of Technology, Graduate ASIC published examples here is 1-20 months
- 2022-05-22 16:09:28下载
- 积分：1
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zhaozhou_verilog
usb3.0 物理层仿真，verilog编程(Start the physical simulation)
- 2014-04-04 11:49:09下载
- 积分：1
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imply logic
由忆阻器机制设计蕴含逻辑，内含testbench仿真文件(Design implied logic by memristor mechanism, including testbench simulation file)
- 2019-04-24 15:42:24下载
- 积分：1
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verilog 写的 “梁祝”乐曲演奏电路
verilog 写的 “梁祝”乐曲演奏电路-verilog wrote " The Butterfly Lovers" music concert circuit
- 2022-02-03 08:31:54下载
- 积分：1
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buffer for in/out data.
buffer for in/out data.
- 2023-02-22 20:05:04下载
- 积分：1
