-
bit7_Binary_to_BCD_LED
二进制转十进制BCD码 Verilog语言 quartusII(Binary to decimal BCD code Verilog language quartusII)
- 2013-09-14 16:49:39下载
- 积分：1
-
a
说明： 利用FPGA实现SDH开销中帧头A1A2的检测(FPGA implementation using SDH overhead in the frame header detection of A1A2)
- 2010-05-25 21:17:03下载
- 积分：1
-
Counter1s
counter number one to nine after 1s
- 2014-10-22 15:54:51下载
- 积分：1
-
Block-Landscape-Design
3D的效果，逼真的视觉享受，真实的场景。(3D effects, realistic visual experience, the real scene.)
- 2014-06-10 19:28:29下载
- 积分：1
-
dac_spi
DA9125 配置spi程序 正弦波产生(DA9125 configuration spi program sine wave generated)
- 2017-05-27 20:17:40下载
- 积分：1
-
VHDL-the-count
利用VHDL 硬件描述语言设计一个0~9999 的加法计数器。根据一定频率的触发
时钟，计数器进行加计数，并利用数码管进行显示，当计数到9999 时，从0 开始重新计数(Use of VHDL hardware description language design a 0 ~ 9999 addition counter. According to a certain frequency of the trigger
The clock, counter add count, and use digital pipes to show that when the count to 9999, starting from 0 to count
)
- 2012-01-13 14:01:38下载
- 积分：1
-
jisuanqishijianxianshi
基于FPGA编写一个时间显示，计数功能，年月显示的程序，(FPGA-based preparation of a time display, counting, years show program,)
- 2011-08-30 16:00:48下载
- 积分：1
-
submodule
verilog 双模块算术平均值计算模块，子模块在时钟上升沿技术，高层模块根据当前计数值计算算数平均(verilog double module arithmetic mean calculation module, sub-module in the clock rising edge technology, high-level module is calculated based on arithmetic average of the current count)
- 2011-01-05 22:49:16下载
- 积分：1
-
一个在Xilinx spartan3实现的时钟，具有时分秒的计时显示以及年月日的显示，很有参考价值
一个在Xilinx spartan3实现的时钟，具有时分秒的计时显示以及年月日的显示，很有参考价值-A Xilinx spartan3 realize the clock, with time-accurate time display and date display, a good reference
- 2022-08-12 21:17:53下载
- 积分：1
-
dct
基于FPGA的图像压缩算法程序，自己写的，可以参考一下(FPGA-based image compression algorithm, write your own, you can refer to)
- 2011-10-23 00:54:17下载
- 积分：1
