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用VHDL实现十六位移位乘法器 才有移位相加法来实现
用VHDL实现十六位移位乘法器 才有移位相加法来实现-Use VHDL to achieve 16-bit shift multiplier shift only the sum of law to achieve
- 2022-04-17 17:23:11下载
- 积分：1
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apb_spi
Simple SPI interface realization on Verilog HDL with parameterized FIFO and APB interface
- 2021-04-06 16:19:02下载
- 积分：1
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4x4键盘模块。这个文件包括普通的键盘设计方案说明和相关的原程序。...
4x4键盘模块。这个文件包括普通的键盘设计方案说明和相关的原程序。-4x4 keyboard module. The documents include ordinary keyboard design program descriptions and procedures related to the original.
- 2022-01-26 02:27:17下载
- 积分：1
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用于实现sin，cos三角函数计数的VHDL程序代码
用于实现sin，cos三角函数计数的VHDL程序代码-towards sin, cos trigonometry count VHDL code
- 2022-01-25 23:34:00下载
- 积分：1
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VGA的IP核，下载即可用，解压到指定目录下就可以了，参照里面的read me....
VGA的IP核，下载即可用，解压到指定目录下就可以了，参照里面的read me.-VGA
- 2022-02-02 20:02:28下载
- 积分：1
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Single-CPU
说明： 简单的单周期CPU设计，实现的指令有：算术运算指令、逻辑运算指令、移位指令、比较指令、存储器读/写指令、分支指令、跳转指令、停机指令。(Simple single-cycle CPU design,The instructions implemented are as follows:Arithmetic operation instruction, logical operation instruction, shift instruction, comparison instruction, memory read/write instruction, branch instruction, jump instruction, stop instruction.)
- 2020-06-16 12:28:32下载
- 积分：1
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eda
EDA 正弦信号发生器：正弦信号发生器的结构有四部分组成，如图1所示。20MHZ经锁相环PLL20输出一路倍频的32MHZ片内时钟,16位计数器或分频器CNT6，6位计数器或地址发生器CN6，正弦波数据存储器data_rom。另外还需D/A0832（图中未画出）将数字信号转化为模拟信号。此设计中利用锁相环PLL20输入频率为20MHZ的时钟，输出一路分频的频率为32MHZ的片内时钟，与直接来自外部的时钟相比，这种片内时钟可以减少时钟延时和时钟变形，以减少片外干扰 还可以改善时钟的建立时间和保持时间，是系统稳定工作的保证。CNT6用来将32MHZ进行8分频得到4096HZ的频率提供给CN6与data_rom时钟信号。由CLK端输入20MHZ的时钟信号，在DOUT端就可输出稳定的正弦信号。(Sine signal generator has the structure of four parts, as shown in figure 1 below. The 20 MHZ phase lock loop PLL20 output all the way of frequency doubled within 32 MHZ slice clock, 16 counter or prescaler CNT6, six counter or address generator CN6, sine data storage data_rom. In addition to D/A0832 (shown in not draw) will digital signal into analog signals. This design using the phase lock loop PLL20 input frequency for 20 MHZ clock, the output of the frequency of all points frequency of 32 pieces (MHZ clock, and comes directly from the external clock, compared to this piece of clock can reduce the clock in delay and clock deformation, to reduce the interference of Can also improve the establishment of the clock time and keep time, is the system stability of assurance. CNT6 used to will and to 8 MHZ get 4096 HZ dividing the frequency to provide CN6 and data_rom clock signal. The input by CLK 20 MHZ clock signal, in DOUT end can output stable sine signals.
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- 2021-03-07 15:49:29下载
- 积分：1
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FPGA PWM输入与输出
自己写的pwm占空比采集与输出 但是没有计算占空比，如果又需要可以自己修改计算并显示占空比，该程序已经测试过了，可以使用，拿出来供大家分享，新手写的如有不足请大牛带飞。
- 2022-01-28 02:10:47下载
- 积分：1
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VHDL黄金版，本人费了九牛才找到，帮助初学者入门
VHDL黄金版，本人费了九牛才找到，帮助初学者入门-VHDL version, I spent nine cattle to find help beginners entry
- 2022-05-26 12:22:32下载
- 积分：1
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入门，verilog语言，实现字符型液晶1602的显示，及按键控制
入门，verilog语言，实现字符型液晶1602的显示，及按键控制-verilog
- 2022-07-19 01:27:34下载
- 积分：1
