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scan_led
FPGA扫描LED显示灯，动态扫描,进行流水显示(FPGA Scan LED indicator lights, dynamic scanning, make the water show)
- 2015-02-16 18:02:16下载
- 积分：1
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fft64
verilog hdl 编写的64点fft代码，适合很多芯片(coded by verilog hdl that implement 64 point fft, suite to many core)
- 2020-12-12 21:19:16下载
- 积分：1
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10_100fsrb.pdf
Ethernet Media Access Controller
- 2014-04-30 19:56:17下载
- 积分：1
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yiweijicunq
说明： 16位右移位寄存器
下面描述的是一个位宽为16位的右移位寄存器，实际具有环形移位的功能，是在右移位寄存器的基础上将最低位的输出端接到最高位的输入端构成的。其功能为当时钟上升沿到达时，输入信号的最低位移位到最高位，其余各位依次向右移动一位。(16-bit right shift register
The following description is a right shift register with a bit width of 16 bits. It actually has the function of circular shift. It is based on the right shift register, which connects the lowest bit output terminal to the highest bit input terminal. Its function is that when the rising edge of the clock arrives, the lowest displacement of the input signal reaches the highest position, and the rest of you move one bit to the right in turn.)
- 2020-08-18 09:58:21下载
- 积分：1
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is done in the laboratory in the loss of 60 counts, and LED show.
是我们在在实验室做的摸60计数，并用LED显示出来。-is done in the laboratory in the loss of 60 counts, and LED show.
- 2022-03-21 19:17:50下载
- 积分：1
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这个是专门用在ALtera第二代PLD MAXII上的16位微处理器IP核，文档齐全...
这个是专门用在ALtera第二代PLD MAXII上的16位微处理器IP核，文档齐全-this is the ALtera devoted second-generation PLD MAXII on the 16-bit microprocessor IP core, complete documentation
- 2022-02-21 05:05:05下载
- 积分：1
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navigation
Ship navigation project
- 2014-12-04 18:58:16下载
- 积分：1
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LIP2242CORE_otp_rom
Verilog OTP ROM source code
- 2011-01-31 09:54:45下载
- 积分：1
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以太网MAC core.this是etherenet UDP的应用
ethernet mac core.this is the etherenet udp application
- 2022-02-10 06:08:39下载
- 积分：1
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一个用于锁相环开发的资料，请作为参考！
一个用于锁相环开发的资料，请作为参考！-A phase-locked loop for the development of the information, please as a reference!
- 2022-11-15 16:30:03下载
- 积分：1
