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FPGA——IP_RAM实验
说明: FPGA——IP_RAM实验:
创建IPRAM核,单端口,10位地址线(256字节),8位数据线(每字节8byte),读写使能
input [9:0] address;
input clock;
input [7:0] data;
input wren; //置1则写入
output [7:0] q;
LNXmode:控制LEDC显示
1:mode1,从k1~k3输入data的低4位,ledb计时,从0~f,计时跳变沿读取k1~k3的值,存入RAM
8个数之后,从RAM输出数据,用leda显示,同样每秒变化一次(The experiment of FPGA-IP_RAM:
Create IPRAM core, single port, 10 bit address line (256 bytes), 8 bit data line (8 byte per byte), read and write enablement)
- 2020-06-22 04:20:02下载
- 积分:1
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ArhivaAdrian
Anticipated Adder for Xilinx
- 2011-11-15 06:57:02下载
- 积分:1
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__keyBoard
vhdl编写的4X4键盘扫描程序,可以有效的消除抖动,并且提供蜂鸣器输出。(VHDL prepared 4X4 keyboard scanner, you can effectively eliminate jitter and provide buzzer output.)
- 2007-10-24 09:11:11下载
- 积分:1
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14_SDRAM
说明: 高速流水的SDRAM控制器,最高速度可达速度在200M左右(high speed SDRAM controller)
- 2019-06-17 18:43:54下载
- 积分:1
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ppm
ppm调制的verilog代码 可实现ppm调制(ppm modulation verilog code ppm modulation)
- 2012-10-23 11:29:33下载
- 积分:1
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beipin_test
实现任意倍数的倍频,帮助大家解决VHDL倍频问题,(The realization of arbitrary multiples of the octave, octave VHDL help people solve problems,)
- 2021-03-24 17:19:14下载
- 积分:1
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实光电码盘的输出数据的四倍频,使码盘输出精度提高四倍。...
实光电码盘的输出数据的四倍频,使码盘输出精度提高四倍。-real photoelectric encoder output data of the four frequency, accuracy encoder output increased by four times.
- 2022-01-23 10:41:40下载
- 积分:1
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verilog基础练习,介绍怎样编写测试文件和仿真
verilog基础练习,介绍怎样编写测试文件和仿真-Verilog based on exercises, how to introduce the preparation of test documentation and simulation
- 2022-01-28 18:39:08下载
- 积分:1
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verilogexample
verilog学习资料。附带简单的源代码列子,可以直接使用和仿真。(verilog learning materials. Source code with a simple Lie Zi, and simulation can be used directly.)
- 2011-05-26 11:53:24下载
- 积分:1
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cla - Copy
ADDER USING VERILOG ADDER WITH VERILOG VERILOG ADDER
- 2019-03-19 01:35:37下载
- 积分:1