-
pn sequence generator
本设计是一个伪随机数发生器。此设计；
- 2023-02-23 15:45:04下载
- 积分：1
-
这时manchesite编码，VERILOG语言，VHDL的找本站我发的帖子
这时manchesite编码，VERILOG语言，VHDL的找本站我发的帖子-manchesite time coding, VERILOG language, VHDL I find a site in a posting
- 2023-07-15 16:55:02下载
- 积分：1
-
本例为ADC0809接口电路VHDL程序原代码
本例为ADC0809接口电路VHDL程序原代码-The ADC0809 Interface Circuit Example for VHDL program source code
- 2022-05-19 18:28:38下载
- 积分：1
-
24_Timer
说明： 使用Verilog编写的24位定时器，具有apb 总线接口，可以设置工作方式和计数初值。(The 24-bit timer written by Verilog has APB bus interface, which can set working mode and count initial value.)
- 2021-04-27 21:38:44下载
- 积分：1
-
ROM模块，功能在于，是创建一个简易的rom模块
ROM模块，功能在于，是创建一个简易的rom模块-rom
- 2022-03-31 16:48:46下载
- 积分：1
-
DE2_115_SD_Card_Audio_Player
该代码实现了对SD 卡的读写操作，是一个较好的范例。(The code achieves access reading SD CARD based on DE-2，It is
a good example。)
- 2012-08-14 00:29:47下载
- 积分：1
-
实验九 计算机核心（CPU+RAM）的设计与实现
计算机组成原理的CPU实验，基于quartus平台(CPU experiment of computer organization principle, based on quartus platform)
- 2018-06-09 11:13:43下载
- 积分：1
-
VHDL实现SPI功能源代码
VHDL实现SPI功能源代码
-- The SPI bus is a 3 wire bus that in effect links a serial shift
-- register between the "master" and the "slave". Typically both the
-- master and slave have an 8 bit shift register so the combined
-- register is 16 bits. When an SPI transfer takes place, the master and
-- slave shift their shift registers 8 bits and thus exchange their 8
-- bit register values.-SPI realize the functional VHDL source code The SPI bus is a 3 wire bus that in effect links a serial shift register between the
- 2022-01-26 00:50:40下载
- 积分：1
-
modulation-and-demodulation
通过verilog语言实现各种基本信号的调制解调过程，包括2psk,qpsk,ppm(Realize the modulation and demodulation process of various basic signals through verilog language, including 2psk, qpsk, ppm)
- 2018-04-26 21:52:04下载
- 积分：1
-
简单的APB I2S接口
简单的apb i2s接口，verilog代码，包括rtl实现和testbench(apb i2s interface . coded by Verilog. including rtl and testbench)
- 2019-01-18 16:52:05下载
- 积分：1
