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UART异步串行通信协议的源代码，采用VHDL语言…
uart异步串口通信协议的源代码，用vhdl语言编写，并且有完整得测试文件-UART asynchronous serial communication protocol source code, using VHDL language, and may have a complete test file
- 2022-03-20 22:18:17下载
- 积分：1
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zichengxu
一些非常有用的程序，均经过调试，让大家一块共享。(Some very useful procedure, have been testing, so that everyone shared one.)
- 2009-07-10 13:48:14下载
- 积分：1
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last
verilog，FPGA的TDC电路设计(verilog ，TDC base on FPGA)
- 2021-01-04 18:48:54下载
- 积分：1
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mmuart
简单uart，verilog语言编写，已经经过测试，有需要的可以看看(Simple uart, Verilog language, has been tested, you can see if you need it)
- 2020-06-23 20:00:01下载
- 积分：1
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VHDL 0~
程序用VHDL实现：
利用一秒定时测量频率
并且显示，范围0~-VHDL 0~
- 2022-05-15 03:55:50下载
- 积分：1
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AWGN_VerilogDesign-master
加性高斯白噪声生成的VERILOG实现，包含所有的testbench文件。可直接使用(Additive white gaussian noise generated VERILOG realized, including all testbench files. Can be used directly)
- 2021-01-14 19:18:46下载
- 积分：1
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The use of long
利用电话远程系统，通过密码验证来实现对家庭电器的智能控制。-The use of long-distance telephone system, via a password to verify the implementation of the intelligent control of household electrical appliances.
- 2022-01-31 17:55:43下载
- 积分：1
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src
说明： 假设每个从设备中有可访问APB寄存器16个，位宽均为32比特，16个寄存器的访问地址计算方式为 基址 + 寄存器编号左移２位（byte 偏移）(Assuming that there are 16 accessible APB registers in each slave device, the bit width is 32 bits, and the access address of 16 registers is calculated by base address + register number left shift 2 bits (byte offset).)
- 2020-12-15 13:49:14下载
- 积分：1
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用VHDL语言编写的AT24C02程序，并用数码管显示，本程序已经经过本人测试过，很好用...
用VHDL语言编写的AT24C02程序，并用数码管显示，本程序已经经过本人测试过，很好用-The AT24C02 is available VHDL language program, and use digital tube display, this procedure has been tested himself, very good to use--
- 2022-04-22 03:40:31下载
- 积分：1
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tcp_ip_core_w_dhcp_latest.tar
以太网协议 TCP/IP/DHCP协议verilog实现(Ethernet IP/TCP/DHCP verilog source code)
- 2018-08-23 14:35:01下载
- 积分：1
