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用VHDL和约翰逊状态编码状态的有限状态机
An FSM using VHDL and Johnson state encoding for states
- 2022-04-27 12:30:31下载
- 积分：1
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8b10b_encoder_and_decoder
可编程器件厂商Altera出品的8b10b编码器源代码(Giga8b10b v10)
- 2021-01-22 16:08:40下载
- 积分：1
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Verilog_Ip_RAM
说明： altera ram ip教程。对RAM进行读写操作，写32个数据到RAM中，再将写入的32个数据从RAM中读出。(altera ram ip.write data to ram and read the data from the ram.)
- 2020-08-17 11:38:21下载
- 积分：1
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testbench
说明： altera 最新的CYCLONE IV的pci-e核的testbench，VHDL源程序。(altera latest CYCLONE IV of the pci-e core testbench, VHDL source code.)
- 2010-04-22 10:20:24下载
- 积分：1
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ser_to_parr
很有用的10bit串并转换verilog程序，需要的可以拿去参考下，在quartusII上已验证过(Useful 10bit string and convert verilog program, need to take a reference, has been verified in quartusII)
- 2012-05-21 16:21:22下载
- 积分：1
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This application note explains the process of eveloping and debugging a hardware...
This application note explains the process of eveloping and debugging a hardware abstraction layer (HAL) software device driver, to aid device driver development for the HAL of the Altera Nios® II system. The various software development stages are illustrated using the Altera_Avalon_UART as an example hardware device, and an example of a HAL software device driver called my_uart.-This application note explains the process of eveloping and debugging a hardware abstraction layer (HAL) software device driver, to aid device driver development for the HAL of the Altera Nios® II system. The various software development stages are illustrated using the Altera_Avalon_UART as an example hardware device, and an example of a HAL software device driver called my_uart.
- 2022-01-23 11:16:04下载
- 积分：1
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[verilog]dcfifo_256x32
双时钟域FIFO(This is self-defined Dual-Clock FIFO, using logic lut resources.
Dual-Clock FIFO,
Depth: 256
Width: 32
USEDW: Y
FULLL:Y
EMPTY:Y)
- 2017-05-10 13:25:41下载
- 积分：1
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移位乘法器的输入为两个4位操作数a和b，启动乘法器由stb控制，clk信号提供系统定时。乘法器的结果为8位信号result,乘法结束后置信号done为1....
移位乘法器的输入为两个4位操作数a和b，启动乘法器由stb控制，clk信号提供系统定时。乘法器的结果为8位信号result,乘法结束后置信号done为1.
乘法算法采用原码移位乘法，即对两个操作数进行逐位的移位相加，迭代4次后输出结果。具体算法：
1. 被乘数和乘数的高位补0，扩展成8位。
2. 乘法依次向右移位，并检查其最低位，如果为1，则将被乘数和部分和相加，然后将被乘数向左移位；如果为0，则仅仅将被乘数向左移位。移位时，被乘数的低端和乘数的高端均移入0.
3. 当乘数变成全0后，乘法结束。
-err
- 2022-04-10 04:29:26下载
- 积分：1
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time_echo
GPS接收机相关器中关于积分清零模块、历元计数模块、时钟模块、以及整个相关器(accumulator、epoch counter、time base、gps baseband)
- 2015-08-28 23:47:56下载
- 积分：1
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vhdl波形发生程序.实现4种常见波形正弦、三角、锯齿、方波（A、B）的频率、幅度可控输出（方波
A的占空比也是可控的），可以存储任意波形特征数据并能重现该...
vhdl波形发生程序.实现4种常见波形正弦、三角、锯齿、方波（A、B）的频率、幅度可控输出（方波
A的占空比也是可控的），可以存储任意波形特征数据并能重现该波形，还可完成
各种波形的线形叠加输出。
-vhdl waveform occurred procedures. 4 achieve common sinusoidal waveform, 1.30, sawtooth, square-wave (A, B) the frequency and amplitude control output (square A duty cycle is also controllable), can store data of arbitrary waveform characteristics and able to reproduce the waveform, but also through a variety of linear superposition of the waveform output.
- 2023-03-26 13:10:03下载
- 积分：1
