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简易数字钟实验报告

于 2023-01-21 发布 文件大小:518.98 kB
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在学习verilog语言及数电的相关知识后,运用所学知识及查阅资料完成对简易数字钟的设计,以巩固以前所学知识,提高解决和分析问题的能力以及掌握稍复杂逻辑电路的设计方法;深刻理解verilog语言的思路,并进一步掌握操作BASYS2板的使用;掌握计数器的设计方法,模块之间的协调方式,了解电路设计层次。       构造一个24小时制的数字钟,要求能显示时、分、秒(用数码管加LED来完成),能利用板上的微动开关作时钟的调整,用板上的LED的闪烁作整点报时。

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