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XAPP_585

于 2021-02-04 发布 文件大小:593KB
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代码说明:

  XAPP585 serdes_1_to_7 and serdes_7_to_1 data

文件列表:

XAPP_585
........\readme.txt,8686,2013-10-15
........\ucf
........\...\top5x2_7to1_ddr_rx.ucf,5702,2013-10-15
........\...\top5x2_7to1_ddr_tx.ucf,4521,2013-10-15
........\...\top5x2_7to1_sdr_rx.ucf,5204,2013-10-15
........\...\top5x2_7to1_sdr_tx.ucf,4521,2013-10-15
........\Verilog_macros
........\..............\clock_generator_pll_7_to_1_diff_ddr.v,15176,2013-10-15
........\..............\clock_generator_pll_7_to_1_diff_sdr.v,14005,2013-10-15
........\..............\gearbox_4_to_7.v,7558,2013-10-15
........\..............\n_x_serdes_1_to_7_mmcm_idelay_ddr.v,7937,2013-10-15
........\..............\n_x_serdes_1_to_7_mmcm_idelay_sdr.v,7614,2013-10-15
........\..............\n_x_serdes_7_to_1_diff_ddr.v,4579,2013-10-15
........\..............\n_x_serdes_7_to_1_diff_sdr.v,4483,2013-10-15
........\..............\serdes_1_to_7_mmcm_idelay_ddr.v,34110,2013-10-15
........\..............\serdes_1_to_7_mmcm_idelay_sdr.v,29651,2013-10-15
........\..............\serdes_1_to_7_slave_idelay_ddr.v,22220,2013-10-15
........\..............\serdes_1_to_7_slave_idelay_sdr.v,19783,2013-10-15
........\..............\serdes_7_to_1_diff_ddr.v,14484,2013-10-15
........\..............\serdes_7_to_1_diff_sdr.v,7300,2013-10-15
........\Verilog_testbench
........\.................\tb_top5x2_7to1_ddr.v,4333,2013-10-15
........\.................\tb_top5x2_7to1_sdr.v,4333,2013-10-15
........\Verilog_top_level_examples
........\..........................\top5x2_7to1_ddr_rx.v,5893,2013-10-15
........\..........................\top5x2_7to1_ddr_tx.v,6059,2013-10-15
........\..........................\top5x2_7to1_sdr_rx.v,5856,2013-10-15
........\..........................\top5x2_7to1_sdr_tx.v,5962,2013-10-15
........\VHDL_macros
........\...........\clock_generator_pll_7_to_1_diff_ddr.vhd,14669,2013-10-15
........\...........\clock_generator_pll_7_to_1_diff_sdr.vhd,13329,2013-10-15
........\...........\gearbox_4_to_7.vhd,8672,2013-10-15
........\...........\n_x_serdes_1_to_7_mmcm_idelay_ddr.vhd,13067,2013-10-15
........\...........\n_x_serdes_1_to_7_mmcm_idelay_sdr.vhd,12426,2013-10-15
........\...........\n_x_serdes_7_to_1_diff_ddr.vhd,5875,2013-10-15
........\...........\n_x_serdes_7_to_1_diff_sdr.vhd,5671,2013-10-15
........\...........\serdes_1_to_7_mmcm_idelay_ddr.vhd,38281,2013-10-15
........\...........\serdes_1_to_7_mmcm_idelay_sdr.vhd,32399,2013-10-15
........\...........\serdes_1_to_7_slave_idelay_ddr.vhd,25745,2013-10-15
........\...........\serdes_1_to_7_slave_idelay_sdr.vhd,22715,2013-10-15
........\...........\serdes_7_to_1_diff_ddr.vhd,11213,2013-10-15
........\...........\serdes_7_to_1_diff_sdr.vhd,7989,2013-10-15
........\VHDL_testbench
........\..............\tb_top5x2_7to1_ddr.vhd,6043,2013-10-15
........\..............\tb_top5x2_7to1_sdr.vhd,6043,2013-10-15
........\VHDL_top_level_examples
........\.......................\top5x2_7to1_ddr_rx.vhd,9629,2013-10-15
........\.......................\top5x2_7to1_ddr_tx.vhd,9531,2013-10-15
........\.......................\top5x2_7to1_sdr_rx.vhd,10317,2013-10-15
........\.......................\top5x2_7to1_sdr_tx.vhd,9825,2013-10-15
........\xapp585-lvds-source-synch-serdes-clock-multiplication.pdf,836732,2013-10-15
........\xapp585_ Uncertainties_ tool_ 1.1.xlsx,11126,2013-10-15

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